On 03/19/10 10:47, Ian Bolton wrote:
I mention all this because I was wondering which other architectures
have turned off sched1 for -Os? More importantly, I was wondering
if anyone else had considered creating some kind of clever hybrid
that only uses sched1 when it will increase performance without
increasing register pressure?
http://gcc.gnu.org/ml/gcc-patches/2009-09/msg00003.html
Another problem is that sched1 for architectures with few registers
can
result in reload failure. I tried to fix this in the patch mentioned
above but I am not sure it is done for all targets and all possible
programs. The right solution for this would be implementing hard
register spills in the reload.
I don't think we have so few registers that reload failure will occur,
so it might be worth me trying this.
From what I know of your architecture, it's unlikely. The canonical
case occurs when you have certain instructions that absolutely must use
specific registers and you expose that register's class to asm
writers. There's other ways to trigger, but that's the easiest one.
WRT hard register spills, that's something I worked on last year and a
major component of the second phase of the ira-reload code I'm working
on. While I wasn't setting out to solve the sched1 vs small register
class problems, it gets solved as a byproduct of intelligent spilling.
The implementations I did were quite ugly, but enough to tell me ideas
were sound and give me some insight into how to integrate multiple
spilling techniques.
And just a general note -- the tension between scheduling & register
allocation is a well known problem, but not one that has been solved
within GCC. The sched1, allocate, sched2 is a classic approach to
lessen the impact, but isn't a real solution. I'm sure Vlad can point
you at academic research in this space :-)
jeff
