Hi,
    I am working on a micro controller and trying to port gcc(4.3.2) for it.
    There is insv instruction in our micro controller and I have add
define_insn to machine description file.
    However, the insv instruction can only be generated when the code
is written like below.  If the code is written using logical shift and
    or operators, the insv instruction will not be generated.
    For the statement: x= (x&0xFF00FFFF) | ((i<<16)&0x00FF0000);
    6 RTL instructions are generated after combine pass and 8
instructions are generated in the assembly file.
    Paolo Bonzini said that insv instruction might be synthesized
later by combine. But combine only works on at most 3 instructions and
insv is not generated in such case.
    So exactly when will the insv pattern be recognized and how does
the coding style affect it?
    Is there any open bug report about this?

struct test_foo {
unsigned int a:18;
unsigned int b:2;
unsigned int c:12;
};

struct test_foo x;

unsigned int foo()
{
unsigned int a=x.b;
x.b=2;
return a;
}

Thanks!
fanqifei

Reply via email to