Ian Lance Taylor wrote:
daniel tian <daniel.xnt...@gmail.com> writes:
Yeah. Now I solve the unrecognize RTL problem. cc1 does not crash. And
before I add the second_reload macro. There are two problems happened.
1. there is a RTL code which move the memory data to another memory
location. RTL extracted from file *.23.greg :
(insn 128 127 130 7 (set (mem/i:SI (plus:SI (reg/f:SI 14 R14)
(const_int 28 [0x1c])) [0 nChannels+0 S4 A32])
(mem:SI (plus:SI (reg/f:SI 14 R14)
(const_int 11372 [0x2c6c])) [0 iftmp.0+0 S4 A32])) 8
{store_si} (nil)
(nil))
this is not allowed in my RISC chip. And This doesn't go through the
reload macro. Is this need to solve in secondary reload?
This kind of thing will be generated during reload, but should be
cleaned up during reload. If it is not, it suggests that perhaps you
are not checking REG_OK_STRICT as required, or that your predicates or
constraints are wrong. Or there may be some other explanation.
Also note that the secondary reload code needs to handle the case where
it's passed a pseudo that hasn't been allocated a hard register. I
think he can get that code of code if he's not handling those cases
properly.
However, the most likely cause is reload replacing a pseudo with its
equivalent memory location and the port incorrectly accepting that form
as valid, either because of a problem with REG_OK_STRICT, operand
predicate or constraints, LEGITIMIZE_RELOAD_ADDRESS, etc.
2. Here is the RTL code in file *.23.greg:
(insn:HI 112 218 105 4 (set (reg:SI 5 R5 [78])
(plus:SI (reg:SI 7 R7)
(const_int 2064 [0x810]))) 45 {rice_addsi3}
(insn_list:REG_DEP_TRUE 161 (insn_list:REG_DEP_TRUE 73
(insn_list:REG_DEP_ANTI 79 (nil))))
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 R14)
(const_int 2076 [0x81c]))
(nil)))
which is not legal in my risc chip. In MD file, I 've already defined
the addsi instruction pattern which only allows the 2nd operand with
less than 512. I don't know how did this happen. I mean I do know this
RTL comes from gcc optimization combination, but how it , which should
be an unrecognizable RTL, becomes recognizable RTL. Does it also need
the secondary reload macro to handle?
The insn was recognized as rice_addsi3, so take a good look at that insn
and make sure the predicates and constraints reject the 2064.
Agreed. There may be cases where reload generates this as well when
there's pseudos that don't get hard registers and the pseudos have
equivalent forms. These may indicate more cases that will need
secondary reloads.
Jeff
