Hi:

>> 1) does your machine use cc0?

No. In my RISC chip, there is a status register existed, like ARM. But I now
I didn't write any code to support it, as well as absent cc0 register.
 
>>  2) what pass is producing those subregs?
This is really puzzled me. I just wrote the PROMOTE_MODE like MIPS. 

>>  3) what is your definition of GO_IF_LEGITIMATE_ADDRESS?

Here is my definition of GO_IF_LEGITIMATE_ADDRESS:
#ifndef REG_OK_STRICT
#define RICE_REG_STRICT_P 0
#else /* REG_OK_STRICT */
#define RICE_REG_STRICT_P 1
#endif /* REG_OK_STRICT */

#define GO_IF_LEGITIMATE_ADDRESS(mode,x,label) \
{\
        if (rice_go_if_legitimate_address(mode, x, RICE_REG_STRICT_P))\
                goto label;\
}

int rice_go_if_legitimate_address(enum machine_mode mode,rtx X, int
bIsStrict)
{
        rtx op1,op2;
        enum rtx_code code = GET_CODE (X);
        
        //(Rmem)        #4/2/1  -PRI/PRD/POI/POD        
        if ((code == PRE_INC || code == PRE_DEC)
                        && (GET_MODE_SIZE (mode) <= 4))
        {
                rtx op1;
                op1=XEXP(X, 0);
                if(GET_CODE(op1) == REG)
                        return is_base_reg_strict(REGNO(op1));
                else 
                        return RICE_NO;
        }
        //(Rmem)        {Rx, #UImm8}    -PRI/PRD/POI/POD -W
        if ((code == POST_MODIFY || code == PRE_MODIFY)
           && rice_reg_ok_for_base (XEXP (X, 0), bIsStrict)
           && GET_CODE (XEXP (X, 1)) == PLUS
           && rtx_equal_p (XEXP (XEXP (X, 1), 0), XEXP (X, 0)))
    {
      rtx addend = XEXP (XEXP (X, 1), 1);
      return (rice_if_legitimate_index (mode, addend, bIsStrict));
    }
        
        if(GET_CODE(X) == PLUS)
        {
                //check where the form is like (Rmem)   {Rx, #UImm8}
                return rice_base_index_address(X, bIsStrict); 
        }
        return RICE_NO;
}

BTY: the address mode in my RISC chip is like the following:

        LOADW Rd        (Rs)     Rx/offset(8bits unsigned immediate) 
Which means Rd = (Rs + Rx) 0r Rd = (Rs + imm_8bits). So if the immediate
offset is larger than 255, it should be move into register first.

I think this definition in my port is appropriate.
Any advice?

>>  [I trimmed a bit the list of recipients, sending to the mailing list is
usually enough.]

Ok, I gotta it and will keep attention in future. 

Thanks!
_______________________________________________

Best Regards

Daniel Tian

Mavrix Technology, Inc.
Address:200 Zhangheng Road, #3501, Building 3, Zhangjiang Hi-tech Park,
Shanghai, P.R.China (201204) 

Tel:86(21)51095958 - 8125

Fax:86(21)50277658

email:daniel.t...@mavrixtech.com.cn

www.mavrixtech.com


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