On Mon, May 5, 2008 at 12:23 PM, Pranav Bhandarkar <[EMAIL PROTECTED]> wrote: > Hi Mohammed, > > > > But how can i handle instances like this? Should i be doing insertion > > of nops in reorg pass? > > FWIW, I had worked on a port for VLIW processor about three years back > and IIRC we had used the reorg pass for inserting the nops. I think > if you look at the scheduler dumps you will notice that the scheduler > would have, in all likelihood, accounted for the delay of 1 cycle > between the "lw" and the "add" instructions. Only that you will have > to put the "nop" yourself between these two instructions. > Thanks for your reply. Thats what i am doing right now. But i am not doing in reorg pass but in final_prescan. But things go wrong when the two instructions actually are placed in the delay slots. So after filling the delay slot the instructions are like this
call fun ; has two delay slots lw R0, R8 ; delay slot 1 add R1, R0 ; delay slot 2 Now after final prescan the output is like call fun lw R0, R8 nop add R1, R0 This means 3 instruction in delay slots which can have only 2. So my question was how do i overcome this? Should i do delay slot scheduling myself in reorg pass or is there some other way? Thanks for your time, Regards, Shafi
