Alexandre Oliva wrote:
On Mar 9, 2008, Richard Guenther <[EMAIL PROTECTED]> wrote:
On Sun, 9 Mar 2008, Alexandre Oliva wrote:
AM33/2.0 and H8SX come to mind, although it's been a while since I
dealt with the memory bit-field operations of these two ports to have
the details handy.
Ok, I would expect it a size benefit at most.
I wouldn't think so. Turning a single hardware-optimized instruction
into a series of load, shift, mask, combine, store is unlikely to
benefit just size. Especially considering that these optimized
instructions were introduced in revisions of the processor.
And then, I've failed to see a compelling reason to justify such a
change, that would have the effect of disabling this optimization,
even if it was "just" a size optimization.
Anyway, size and performance are always related because of icache
effects.
