Hi,
On Thu, Dec 18, 2014 at 02:48:46PM -0600, Pat Haugen wrote:
> ;; 128-bit ANDC/ORC
> +;; In the case where rs6000_split_logical is called, the NOT'd operand
> +;; must be opnd1 in order for the split insns to be recognized.
So fix rs6000_split_logical?
> (define_insn_and_split "*boolc<mode>3_internal1"
> [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
> (match_operator:BOOL_128 3 "boolean_operator"
> [(not:BOOL_128
> - (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
> - (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
> + (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
> + (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
This fixes the previously wrong BOOL_REGS_OP[12], you should mention
that somewhere :-)
> "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
> {
> if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
> - return "xxl%q3 %x0,%x1,%x2";
> + return "xxl%q3 %x0,%x2,%x1";
>
> if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
> - return "v%q3 %0,%1,%2";
> + return "v%q3 %0,%2,%1";
Please let's keep operands in assembler order if at all possible.
Segher
