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Return-Path: <wang.deqi...@linaro.org> Received: (qmail 10385 invoked by uid 89); 11 Oct 2014 10:20:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Checked: by ClamAV 0.98.4 on sourceware.org X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.4 required=5.0 tests=BAYES_00,HTML_MESSAGE,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=no version=3.3.2 X-Spam-Status: No, score=2.4 required=5.0 tests=BAYES_00,HTML_MESSAGE,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=no version=3.3.2 X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on sourceware.org X-Spam-Level: ** X-HELO: mail-wg0-f41.google.com Received: from mail-wg0-f41.google.com (HELO mail-wg0-f41.google.com) (74.125.82.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sat, 11 Oct 2014 10:20:26 +0000 Received: by mail-wg0-f41.google.com with SMTP id b13so5673834wgh.24 for <gcc-patches@gcc.gnu.org>; Sat, 11 Oct 2014 03:20:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to :content-type; bh=ZV+cn7M85SJAyC/lgKXSgq1FlZA4QHtJeE6odMvS8j4=; b=D4aA/49I8VWlV6gK96J+Gv6U8hN3IUq8HEzp94KaVcw+wluErKwW90VKc+zDPm6kpR R/mKLl1feMxtcUqmHz4BgmxRbGg+qKPmekcx2xXVGwB913kgY2YO6v5es0yuoVv6iMxC w+tNFTueNncxM17K7aZa4QcsqrRQYrz5sPZeEnw0E/d8r4YeV1la1DeBQo0KY6Zwxr3f GmUyLOeMaVkvhT3r4Ncfx2ScNsXQJAf5WwC8Z3DSbhtgAnm1IfDMXZikMnkHL9UpsvCL VXuj5b/GRHdTZvMeHgd3ubrHsM37gS8DWRCNf3OxtmP9WY6TwgCDRzzwR2KF4hV4YPOM UMuQ== X-Gm-Message-State: ALoCoQmGcsmcyFnMMvgfdvwabn/UfX5Ind+om2ZI3U/wCQ9pzo4ZlC7OQJPw4k1udvrKVN0h7IkL MIME-Version: 1.0 X-Received: by 10.180.91.170 with SMTP id cf10mr9622981wib.70.1413022823640; Sat, 11 Oct 2014 03:20:23 -0700 (PDT) Received: by 10.194.97.12 with HTTP; Sat, 11 Oct 2014 03:20:23 -0700 (PDT) Date: Sat, 11 Oct 2014 11:20:23 +0100 Message-ID: <cadf_bowznqfwgd_bjseof4m+ccmp8_vdzecmujlajfs1dgg...@mail.gmail.com> Subject: [testsuite patch] avoid test when compile options is conflict with default mthumb From: Wang Deqiang <wang.deqi...@linaro.org> To: gcc-patches@gcc.gnu.org Content-Type: multipart/alternative; boundary=f46d043c7fac76a54a05052303b1 --f46d043c7fac76a54a05052303b1 Content-Type: text/plain; charset=UTF-8 When testing arm-linux-gnueabihf triple with configure options --with-mode=thumb(that makes -mthumb option default). some testcase is failed with error message "sorry, unimplemented: Thumb-1 hard-float VFP ABI". I found gcc compiler show this error message when : 1. -mthumb is used with -march=armv6 (or armv5e) and -mcpu=xscale 2. the test source have function body. And when -mthumb is the default option of compiler, the dg-skip-if functions can not detect it, There is no xscale check function in target-supports.exp in. so we need to add it . And there are only macros in the test program in check_effective_target_arm* function . no function body, we need to add it too. Here is my patch: 2014-10-08 Wangdeqiang <wangdeqi...@linaro.org> * lib/target-supports.exp (check_effective_target_arm_xscale_ok): New function. (check_effective_target_arm_arch_FUNC_ok): Add test function body. * gcc.target/arm/pr40887.c (dg-require-effective-target): add arm_arch_v5te_ok check * gcc.target/arm/scd42-1.c (dg-require-effective-target): add arm_xscale_ok check * gcc.target/arm/scd42-2.c : Likewise * gcc.target/arm/scd42-3.c : Likewise * gcc.target/arm/g2.c : Likewise * gcc.target/arm/xor-and.c (dg-require-effective-target): add arm_arch_v6_ok check Index: gcc/testsuite/gcc.target/arm/pr40887.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr40887.c (revision 216115) +++ gcc/testsuite/gcc.target/arm/pr40887.c (working copy) @@ -1,6 +1,7 @@ /* { dg-skip-if "need at least armv5" { *-*-* } { "-march=armv[234]*" } { "" } } */ /* { dg-options "-O2 -march=armv5te" } */ /* { dg-final { scan-assembler "blx" } } */ +/* { dg-require-effective-target arm_arch_v5te_ok } */ int (*indirect_func)(int x); Index: gcc/testsuite/gcc.target/arm/scd42-2.c =================================================================== --- gcc/testsuite/gcc.target/arm/scd42-2.c (revision 216115) +++ gcc/testsuite/gcc.target/arm/scd42-2.c (working copy) @@ -5,6 +5,7 @@ /* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ /* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm32 } */ +/* { dg-require-effective-target arm_xscale_ok } */ unsigned load2(void) __attribute__ ((naked)); unsigned load2(void) Index: gcc/testsuite/gcc.target/arm/scd42-3.c =================================================================== --- gcc/testsuite/gcc.target/arm/scd42-3.c (revision 216115) +++ gcc/testsuite/gcc.target/arm/scd42-3.c (working copy) @@ -3,6 +3,7 @@ /* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */ /* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ /* { dg-options "-mcpu=xscale -O" } */ +/* { dg-require-effective-target arm_xscale_ok } */ unsigned load4(void) __attribute__ ((naked)); unsigned load4(void) Index: gcc/testsuite/gcc.target/arm/g2.c =================================================================== --- gcc/testsuite/gcc.target/arm/g2.c (revision 216115) +++ gcc/testsuite/gcc.target/arm/g2.c (working copy) @@ -5,6 +5,7 @@ /* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */ /* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */ /* { dg-require-effective-target arm32 } */ +/* { dg-require-effective-target arm_xscale_ok } */ /* Brett Gaines' test case. */ unsigned BCPL(unsigned) __attribute__ ((naked)); Index: gcc/testsuite/gcc.target/arm/xor-and.c =================================================================== --- gcc/testsuite/gcc.target/arm/xor-and.c (revision 216115) +++ gcc/testsuite/gcc.target/arm/xor-and.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O -march=armv6" } */ /* { dg-prune-output "switch .* conflicts with" } */ +/* { dg-require-effective-target arm_arch_v6_ok } */ unsigned short foo (unsigned short x) { Index: gcc/testsuite/gcc.target/arm/scd42-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/scd42-1.c (revision 216115) +++ gcc/testsuite/gcc.target/arm/scd42-1.c (working copy) @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "" } } */ /* { dg-options "-mcpu=xscale -O" } */ +/* { dg-require-effective-target arm_xscale_ok } */ unsigned load1(void) __attribute__ ((naked)); unsigned load1(void) Index: gcc/testsuite/lib/target-supports.exp =================================================================== --- gcc/testsuite/lib/target-supports.exp (revision 216115) +++ gcc/testsuite/lib/target-supports.exp (working copy) @@ -2721,6 +2721,11 @@ foreach { armfunc armflag armdef } { v4 #if !defined (DEF) #error !DEF #endif + int + main (void) + { + return 0; + } } "FLAG" ] } @@ -2948,6 +2953,23 @@ proc check_effective_target_arm_hf_eabi }] } +# Return 1 if this is an ARM target supporting -mcpu=xscale. +# Some multilibs may be incompatible with this option. +proc check_effective_target_arm_xscale_ok { } { + if { [check_effective_target_arm32] } { + return [check_no_compiler_messages arm_xscale_ok object { + int dummy; + int + main (void) + { + return 0; + } + } "-mcpu=xscale"] + } else { + return 0 + } +} + # Return 1 if this is an ARM target supporting -mcpu=iwmmxt. # Some multilibs may be incompatible with this option. --f46d043c7fac76a54a05052303b1 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable <div dir=3D"ltr">When testing arm-linux-gnueabihf triple with configure opt= ions --with-mode=3Dthumb(that makes -mthumb option default).<br>some testca= se is failed with error message "sorry, unimplemented: Thumb-1 hard-fl= oat VFP ABI".<br>I found gcc compiler show this error message when :<b= r>1. -mthumb is used with -march=3Darmv6 (or armv5e) and -mcpu=3Dxscale<br>= 2. the test source have function body.<br><br>And when -mthumb is the defau= lt option of compiler, the dg-skip-if functions can not detect it,<br>There= is no xscale check function in target-supports.exp in. so we need to add i= t .<br>And there are only macros in the test program in check_effective_tar= get_arm* function . no function body, we need to add it too.<br><br>Here is= my patch:<br><br>2014-10-08=C2=A0 Wangdeqiang=C2=A0 <<a href=3D"mailto:= wangdeqi...@linaro.org">wangdeqi...@linaro.org</a>><br>=C2=A0=C2=A0=C2= =A0 * lib/target-supports.exp (check_effective_target_arm_xscale_ok): New f= unction.<br>=C2=A0=C2=A0=C2=A0 (check_effective_target_arm_arch_FUNC_ok): A= dd test function body.<br>=C2=A0=C2=A0=C2=A0 * gcc.target/arm/pr40887.c (dg= -require-effective-target): add arm_arch_v5te_ok check<br>=C2=A0=C2=A0=C2= =A0 * gcc.target/arm/scd42-1.c (dg-require-effective-target): add arm_xscal= e_ok check<br>=C2=A0=C2=A0=C2=A0 * gcc.target/arm/scd42-2.c : Likewise<br>= =C2=A0=C2=A0=C2=A0 * gcc.target/arm/scd42-3.c : Likewise<br>=C2=A0=C2=A0=C2= =A0 * gcc.target/arm/g2.c : Likewise<br>=C2=A0=C2=A0=C2=A0 * gcc.target/arm= /xor-and.c (dg-require-effective-target): add arm_arch_v6_ok check<br><br>I= ndex: gcc/testsuite/gcc.target/arm/pr40887.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/pr40887.c=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/gcc.targ= et/arm/pr40887.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -1,6 +1= ,7 @@<br>=C2=A0/* { dg-skip-if "need at least armv5" { *-*-* } { = "-march=3Darmv[234]*" } { "" } } */<br>=C2=A0/* { dg-op= tions "-O2 -march=3Darmv5te" }=C2=A0 */<br>=C2=A0/* { dg-final { = scan-assembler "blx" } } */<br>+/* { dg-require-effective-target = arm_arch_v5te_ok } */<br>=C2=A0<br>=C2=A0int (*indirect_func)(int x);<br>= =C2=A0<br>Index: gcc/testsuite/gcc.target/arm/scd42-2.c<br>=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/sc= d42-2.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuit= e/gcc.target/arm/scd42-2.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>= @@ -5,6 +5,7 @@<br>=C2=A0/* { dg-skip-if "Test is specific to the Xsca= le" { arm*-*-* } { "-mcpu=3D*" } { "-mcpu=3Dxscale"= ; } } */<br>=C2=A0/* { dg-skip-if "Test is specific to ARM mode" = { arm*-*-* } { "-mthumb" } { "" } } */<br>=C2=A0/* { dg= -require-effective-target arm32 } */<br>+/* { dg-require-effective-target a= rm_xscale_ok } */<br>=C2=A0<br>=C2=A0unsigned load2(void) __attribute__ ((n= aked));<br>=C2=A0unsigned load2(void)<br>Index: gcc/testsuite/gcc.target/ar= m/scd42-3.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<br>--- g= cc/testsuite/gcc.target/arm/scd42-3.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (revisi= on 216115)<br>+++ gcc/testsuite/gcc.target/arm/scd42-3.c=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 (working copy)<br>@@ -3,6 +3,7 @@<br>=C2=A0/* { dg-skip-if &qu= ot;Test is specific to Xscale" { arm*-*-* } { "-march=3D*" }= { "-march=3Dxscale" } } */<br>=C2=A0/* { dg-skip-if "Test i= s specific to Xscale" { arm*-*-* } { "-mcpu=3D*" } { "-= mcpu=3Dxscale" } } */<br>=C2=A0/* { dg-options "-mcpu=3Dxscale -O= " } */<br>+/* { dg-require-effective-target arm_xscale_ok } */<br>=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <br>=C2=A0unsigned load= 4(void) __attribute__ ((naked));<br>=C2=A0unsigned load4(void)<br>Index: gc= c/testsuite/gcc.target/arm/g2.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/g2.c=C2=A0=C2=A0 (revision= 216115)<br>+++ gcc/testsuite/gcc.target/arm/g2.c=C2=A0=C2=A0 (working copy= )<br>@@ -5,6 +5,7 @@<br>=C2=A0/* { dg-skip-if "Test is specific to the= Xscale" { arm*-*-* } { "-mcpu=3D*" } { "-mcpu=3Dxscale= " } } */<br>=C2=A0/* { dg-skip-if "Test is specific to ARM mode&q= uot; { arm*-*-* } { "-mthumb" } { "" } } */<br>=C2=A0/*= { dg-require-effective-target arm32 } */<br>+/* { dg-require-effective-tar= get arm_xscale_ok } */<br>=C2=A0<br>=C2=A0/* Brett Gaines' test case. *= /<br>=C2=A0unsigned BCPL(unsigned) __attribute__ ((naked));<br>Index: gcc/t= estsuite/gcc.target/arm/xor-and.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/xor-and.c=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/gcc.target/arm/xo= r-and.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -1,6 +1,7 @@<br>= =C2=A0/* { dg-do compile } */<br>=C2=A0/* { dg-options "-O -march=3Dar= mv6" } */<br>=C2=A0/* { dg-prune-output "switch .* conflicts with= " } */<br>+/* { dg-require-effective-target arm_arch_v6_ok } */<br>=C2= =A0<br>=C2=A0unsigned short foo (unsigned short x)<br>=C2=A0{<br>Index: gcc= /testsuite/gcc.target/arm/scd42-1.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/scd42-1.c=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/gcc.target/arm/sc= d42-1.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -2,6 +2,7 @@<br>= =C2=A0/* { dg-do compile } */<br>=C2=A0/* { dg-skip-if "incompatible o= ptions" { arm*-*-* } { "-march=3D*" } { "" } } */<= br>=C2=A0/* { dg-options "-mcpu=3Dxscale -O" } */<br>+/* { dg-req= uire-effective-target arm_xscale_ok } */<br>=C2=A0<br>=C2=A0unsigned load1(= void) __attribute__ ((naked));<br>=C2=A0unsigned load1(void)<br>Index: gcc/= testsuite/lib/target-supports.exp<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D<br>--- gcc/testsuite/lib/target-supports.exp=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/lib/target-sup= ports.exp=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -2721,6 = +2721,11 @@ foreach { armfunc armflag armdef } { v4<br>=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #i= f !defined (DEF)<br>=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #error !DEF<br>=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #endi= f<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 int<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 main (void)<br>+=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {<br>+=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 return 0;<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<br>=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } "FLAG" ]<br>=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<br>=C2=A0<br>@@ -2948,6 +2953,23 @@ = proc check_effective_target_arm_hf_eabi<br>=C2=A0=C2=A0=C2=A0=C2=A0 }]<br>= =C2=A0}<br>=C2=A0<br>+# Return 1 if this is an ARM target supporting -mcpu= =3Dxscale.<br>+# Some multilibs may be incompatible with this option.<br>+p= roc check_effective_target_arm_xscale_ok { } {<br>+=C2=A0=C2=A0=C2=A0 if { = [check_effective_target_arm32] } {<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 return [check_no_compiler_messages arm_xscale_ok object {<br>+=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int dummy;<br>+=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int<br>+=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 main (void)<br>+=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {<br>+=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return 0= ;<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<br>+= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } "-mcpu=3Dxscale"]<br= >+=C2=A0=C2=A0=C2=A0 } else {<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 return 0<br>+=C2=A0=C2=A0=C2=A0 }<br>+}<br>+<br>=C2=A0# Return 1 if thi= s is an ARM target supporting -mcpu=3Diwmmxt.<br>=C2=A0# Some multilibs may= be incompatible with this option.<br></div> --f46d043c7fac76a54a05052303b1--
