Hans Boehm pointed out that we were using dmb sy instead of dmb ish.
Given that the ARM-ARM says that the inner shareability domain is really
the one that contains all PE's controlled by a single hypervisor or
operating system, it would be safe to replace all dmb sy's with dmb ish's.
This is also in line with what we do in the AArch64 backend.
Will apply after a test run tonight on armhf.
regards
Ramana
* config/arm/sync.md (memory_barrier): Use dmb ish.
commit fca60730dee3281db4b688d9029ef08688507843
Author: Ramana Radhakrishnan <ramana.radhakrish...@arm.com>
Date: Fri Sep 26 09:08:20 2014 +0100
Use dmb ish instead of dmb sy for ARM.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 06c4f0a..0614c50 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2014-09-26 Ramana Radhakrishnan <ramana.radhakrish...@arm.com>
+
+ * config/arm/sync.md (memory_barrier): Use dmb ish.
+
2014-09-25 Alexander Ivchenko <alexander.ivche...@intel.com>
Maxim Kuznetsov <maxim.kuznet...@intel.com>
Anna Tikhonova <anna.tikhon...@intel.com>
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index aa8e9ab..2f4f478 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -50,10 +50,9 @@
{
if (TARGET_HAVE_DMB)
{
- /* Note we issue a system level barrier. We should consider issuing
- a inner shareabilty zone barrier here instead, ie. "DMB ISH". */
- /* ??? Differentiate based on SEQ_CST vs less strict? */
- return "dmb\tsy";
+ /* We used to issue a system level barrier. We now issue an
+ inner shareabilty zone barrier here instead, ie. "DMB ISH". */
+ return "dmb\tish";
}
if (TARGET_HAVE_DMB_MCR)
