[PATCH][ARM/AArch64] Improve modeled latency between FP operations and FP->GP register moves

[Kyrill Tkachov]

Hi all,

This patch models the latency of moves between FP and GP registers on 
the A15 and A57 a bit more accurately by splitting the reservations for 
FP->GP and GP->FP moves and adding an appropriate bypass.

Bootstrapped and tested on arm-none-linux-gnueabihf and 
aarch64-none-linux-gnu.

Ok for trunk?

Thanks,
Kyrill

2014-11-11  Kyrylo Tkachov  <kyrylo.tkac...@arm.com>

    * config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp):
    Split into...
    (cortex_a15_gp_to_vfp): ...This.
    (cortex_a15_fp_to_gp): ...And this.
    Define and comment bypass from vfp operations to fp->gp moves.commit c176d3e691f470598a02507fa75a8294da954c3f
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Fri Jun 13 11:11:16 2014 +0100

    [ARM/AArch64] Model FP->GP move stalls

diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md
index 02d4a53..bc09cd6 100644
--- a/gcc/config/arm/cortex-a15-neon.md
+++ b/gcc/config/arm/cortex-a15-neon.md
@@ -655,10 +655,20 @@ (define_insn_reservation "cortex_a15_vfp_cpys" 4
        (eq_attr "type" "fmov"))
   "ca15_issue1,ca15_cx_perm")
 
-(define_insn_reservation "cortex_a15_vfp_to_from_gp" 5
+(define_insn_reservation "cortex_a15_gp_to_vfp" 5
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "f_mcr, f_mcrr, f_mrc, f_mrrc"))
-  "ca15_issue1,ca15_ls1+ca15_ls2")
+       (eq_attr "type" "f_mcr, f_mcrr"))
+  "ca15_issue1,ca15_ls")
+
+(define_insn_reservation "cortex_a15_mov_vfp_to_gp" 5
+  (and (eq_attr "tune" "cortexa15")
+       (eq_attr "type" "f_mrc, f_mrrc"))
+  "ca15_issue1,ca15_ls")
+
+;; Moves from floating point registers to general purpose registers
+;; induce additional latency.
+(define_bypass 10 "cortex_a15_vfp*, cortex_a15_neon*, cortex_a15_gp_to_vfp" "cortex_a15_mov_vfp_to_gp")
+
 
 (define_insn_reservation "cortex_a15_vfp_ariths" 7
   (and (eq_attr "tune" "cortexa15")