> On Oct 31, 2014, at 4:07 AM, Matthew Fortune <matthew.fort...@imgtec.com>
> wrote:
>
> Andrew Pinski <pins...@gmail.com> writes:
>> On Thu, Oct 30, 2014 at 11:30 PM, Zhenqiang Chen <zhenqiang.c...@arm.com>
>> wrote:
>>> Thank you all for the comments. Patch is updated.
>>>
>>> Bootstrap and no make check regression on X86-64.
>>> No make check regression with Cortex-M0 qemu.
>>> No performance changes for coremark, dhrystone, spec2000 and spec2006 on
>>> X86-64 and Cortex-A15.
>>>
>>> For CSiBE, ARM Cortex-M0 result is a little better. A little regression
>> for
>>> MIPS (less than 0.01%).
>>
>> I think I have a fix for MIPS which I need to submit too. The problem
>> is IF_THEN_ELSE is not implemented for mips_rtx_costs.
>>
>> Something like the attached one (though It is not updated for the new
>> cores including octeon3).
>
> This looks OK in principle so I have no objection to the original patch
> from Zhengiang. The MIPS patch can follow on.
>
> Andrew: Are you setting higher costs for octeon to try and avoid the
> conversion owing to high latency for MOV[NZ] etc in octeon*?
Yes. In fact I was doing it for the higher latency on octeon 2 than Octeon 1/+.
I saw a small improvement with that, using other instructions in one or two
cases which be scheduled with other code.
> Should that
> be conditional on speed vs size?
Yes though I thought we had a variable for size too.
Thanks,
Andrew
>
> Thanks,
> Matthew
