Ooops, attached.
commit e48d59399722ce8316d4b1b4f28b40d87b1193fa
Author: Alan Lawrence <alan.lawre...@arm.com>
Date: Tue Oct 7 15:28:47 2014 +0100
PowerPC v2 (but not paired.md)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 02ea142..92bb5d0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2596,35 +2596,22 @@
operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
})
-(define_expand "reduc_splus_<mode>"
- [(set (match_operand:VIshort 0 "register_operand" "=v")
+(define_expand "reduc_plus_scal_<mode>"
+ [(set (match_operand:<VI_scalar> 0 "register_operand" "=v")
(unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
UNSPEC_REDUC_PLUS))]
"TARGET_ALTIVEC"
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx vtmp1 = gen_reg_rtx (V4SImode);
- rtx dest = gen_lowpart (V4SImode, operands[0]);
+ rtx vtmp2 = gen_reg_rtx (<MODE>mode);
+ rtx dest = gen_lowpart (V4SImode, vtmp2);
+ HOST_WIDE_INT last_elem = GET_MODE_NUNITS (<MODE>mode) - 1;
emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
- DONE;
-})
-
-(define_expand "reduc_uplus_v16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
- UNSPEC_REDUC_PLUS))]
- "TARGET_ALTIVEC"
-{
- rtx vzero = gen_reg_rtx (V4SImode);
- rtx vtmp1 = gen_reg_rtx (V4SImode);
- rtx dest = gen_lowpart (V4SImode, operands[0]);
-
- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
- emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
- emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
+ rs6000_expand_vector_extract (operands[0], vtmp2, last_elem);
DONE;
})
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 237724e..54b18aa 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -81,7 +81,7 @@
;; Vector reduction code iterators
(define_code_iterator VEC_reduc [plus smin smax])
-(define_code_attr VEC_reduc_name [(plus "splus")
+(define_code_attr VEC_reduc_name [(plus "plus")
(smin "smin")
(smax "smax")])
@@ -1077,18 +1077,20 @@
;; Vector reduction expanders for VSX
-(define_expand "reduc_<VEC_reduc_name>_v2df"
- [(parallel [(set (match_operand:V2DF 0 "vfloat_operand" "")
- (VEC_reduc:V2DF
- (vec_concat:V2DF
- (vec_select:DF
- (match_operand:V2DF 1 "vfloat_operand" "")
- (parallel [(const_int 1)]))
- (vec_select:DF
- (match_dup 1)
- (parallel [(const_int 0)])))
- (match_dup 1)))
- (clobber (match_scratch:V2DF 2 ""))])]
+(define_expand "reduc_<VEC_reduc_name>_scal_v2df"
+ [(parallel [(set (match_operand:DF 0 "vfloat_operand" "")
+ (vec_select:DF
+ (VEC_reduc:V2DF
+ (vec_concat:V2DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "vfloat_operand" "")
+ (parallel [(const_int 1)]))
+ (vec_select:DF
+ (match_dup 1)
+ (parallel [(const_int 0)])))
+ (match_dup 1))
+ (parallel [(const_int 1)])))
+ (clobber (match_scratch:DF 2 ""))])]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"")
@@ -1099,13 +1101,16 @@
; is to allow us to use a code iterator, but not completely list all of the
; vector rotates, etc. to prevent canonicalization
-(define_expand "reduc_<VEC_reduc_name>_v4sf"
- [(parallel [(set (match_operand:V4SF 0 "vfloat_operand" "")
- (VEC_reduc:V4SF
- (unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
- (match_operand:V4SF 1 "vfloat_operand" "")))
+(define_expand "reduc_<VEC_reduc_name>_scal_v4sf"
+ [(parallel [(set (match_operand:SF 0 "vfloat_operand" "")
+ (vec_select:SF
+ (VEC_reduc:V4SF
+ (unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
+ (match_operand:V4SF 1 "vfloat_operand" ""))
+ (parallel [(const_int 3)])))
(clobber (match_scratch:V4SF 2 ""))
- (clobber (match_scratch:V4SF 3 ""))])]
+ (clobber (match_scratch:V4SF 3 ""))
+ (clobber (match_scratch:V4SF 4 ""))])]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"")
