Hello,
This patch further extends maxmin patterns.
Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.
Is it ok for trunk?
gcc/
* config/i386/sse.md
(define_insn "*<code><mode>3_finite<mask_name><round_saeonly_name>"):
Fix pattern conditions order.
(define_insn "*sse4_1_<code><mode>3<mask_name>"): Add masking.
(define_insn "*sse4_1_<code><mode>3<mask_name>"0: Ditto.
--
Thanks, K
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 25bf3d8..a833cd9 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1898,8 +1898,8 @@
(match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v")
(match_operand:VF 2 "<round_saeonly_nimm_predicate>"
"xm,<round_saeonly_constraint>")))]
"TARGET_SSE && flag_finite_math_only
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
- && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
+ && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
v<maxmin_float><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}"
@@ -10209,15 +10209,17 @@
}
})
-(define_insn "*sse4_1_<code><mode>3"
- [(set (match_operand:VI14_128 0 "register_operand" "=x,x")
+(define_insn "*sse4_1_<code><mode>3<mask_name>"
+ [(set (match_operand:VI14_128 0 "register_operand" "=x,v")
(smaxmin:VI14_128
- (match_operand:VI14_128 1 "nonimmediate_operand" "%0,x")
- (match_operand:VI14_128 2 "nonimmediate_operand" "xm,xm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ (match_operand:VI14_128 1 "nonimmediate_operand" "%0,v")
+ (match_operand:VI14_128 2 "nonimmediate_operand" "xm,vm")))]
+ "TARGET_SSE4_1
+ && <mask_mode512bit_condition>
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
- vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ vp<maxmin_int><ssemodesuffix>\t{%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1,*")
@@ -10290,15 +10292,17 @@
}
})
-(define_insn "*sse4_1_<code><mode>3"
- [(set (match_operand:VI24_128 0 "register_operand" "=x,x")
+(define_insn "*sse4_1_<code><mode>3<mask_name>"
+ [(set (match_operand:VI24_128 0 "register_operand" "=x,v")
(umaxmin:VI24_128
- (match_operand:VI24_128 1 "nonimmediate_operand" "%0,x")
- (match_operand:VI24_128 2 "nonimmediate_operand" "xm,xm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ (match_operand:VI24_128 1 "nonimmediate_operand" "%0,v")
+ (match_operand:VI24_128 2 "nonimmediate_operand" "xm,vm")))]
+ "TARGET_SSE4_1
+ && <mask_mode512bit_condition>
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
- vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ vp<maxmin_int><ssemodesuffix>\t{%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1,*")
