On Fri, Sep 26, 2014 at 4:09 PM, Kirill Yukhin <kirill.yuk...@gmail.com> wrote: > Hello, > This patch introduces patterns for vpmaddubsw and vdbpsadbw > insn. > > Bootstrapped. > AVX-512* tests on top of patch-set all pass > under simulator. > > Is it ok for trunk? > > gcc/ > * config/i386/sse.md > (define_c_enum "unspec"): Add UNSPEC_DBPSADBW, UNSPEC_PMADDUBSW512. > (define_insn "avx512bw_pmaddubsw512<mode><mask_name>"): New. > (define_insn "<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>"): > Ditto. > -- > Thanks, K > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 9835234..601373b 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -130,6 +130,8 @@ > UNSPEC_SHA256RNDS2 > > ;; For AVX512BW support > + UNSPEC_DBPSADBW > + UNSPEC_PMADDUBSW512 > UNSPEC_PSHUFHW > UNSPEC_PSHUFLW > UNSPEC_CVTINT2MASK > @@ -13401,6 +13403,19 @@ > (set_attr "prefix" "vex") > (set_attr "mode" "OI")]) > > +;; Unspec version for intrinsics. > +(define_insn "avx512bw_pmaddubsw512<mode><mask_name>" > + [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") > + (unspec:VI2_AVX512VL > + [(match_operand:<dbpsadbwmode> 1 "register_operand" "v") > + (match_operand:<dbpsadbwmode> 2 "nonimmediate_operand" "vm")] > + UNSPEC_PMADDUBSW512))] > + "TARGET_AVX512BW" > + "vpmaddubsw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"; > + [(set_attr "type" "sseiadd") > + (set_attr "prefix" "evex") > + (set_attr "mode" "XI")]) > +
Can the one above be described using standard RTX, perhaps something similar to avx2_pmaddubsw256? > (define_insn "ssse3_pmaddubsw128" > [(set (match_operand:V8HI 0 "register_operand" "=x,x") > (ss_plus:V8HI > @@ -18097,6 +18112,21 @@ > [(set_attr "prefix" "evex") > (set_attr "mode" "<ssescalarmode>")]) > > +(define_insn "<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>" > + [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") > + (unspec:VI2_AVX512VL > + [(match_operand:<dbpsadbwmode> 1 "register_operand" "v") > + (match_operand:<dbpsadbwmode> 2 "nonimmediate_operand" "vm") > + (match_operand:SI 3 "const_0_to_255_operand")] > + UNSPEC_DBPSADBW))] > + "TARGET_AVX512BW" > + "vdbpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}" > + [(set_attr "isa" "avx") > + (set_attr "type" "sselog1") > + (set_attr "length_immediate" "1") > + (set_attr "prefix" "evex") > + (set_attr "mode" "<sseinsnmode>")]) > + > (define_insn "clz<mode>2<mask_name>" > [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") > (clz:VI48_AVX512VL