Hi all we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to revision 214896 as r215060. We have also backported this set of revisions:
r211717 as r214313 : [AArch32] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook r212927 as r214314 : [AArch32] Enable arm target in ira-shrinkwrap-prep* testcases r212978 as r214739 : Testsuite: fix check_effective_target_arm_nothumb r212989 as r214312 : PR 61876: Do not convert cast + __builtin_round into __builtin_lround unless -fno-math-errno is used r213304 as r214314 : [AArch64] Fix Thumb2 testsuite fallout r213378 as r214502 : [AArch64_be] Fix vec_select hi/lo mask confusions. r213379 as r214504 : [AArch64_be] Don't fold reduction intrinsics r213485 as r214505 : [AArch64][1/2] Fix offset glitch in load reg pair pattern r213486 as r214505 : fix ChangeLog for 213485 r213487 as r214505 : [AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insns r213488 as r214506 : [AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hook r213489 as r214506 : add missing testcase for 213488 r213490 as r214507 : [AArch64] Removed unused get_lane and dup_lane builtins. r213551 as r214509 : [sched-deps] Generalise usage of macro fusion to work on any two insns r213556 as r214509 : Fix wrong ChangeLog date from 213551 r213557 as r214511 : [doc] Document clrsb optab and fix some inconsistencies r213627 as r214516 : [AArch64] Some aarch64-builtins.c cleanup. r213628 as r214312 : [convert.c] PR 61876: Guard transformation to lrint by -fno-math-errno r213630 as r214512 : [AArch32] Adjust clz, rbit and rev patterns for -mrestrict-it r213632 as r214513 : [AArch32/AArch64] Add CRC32 scheduling information to Cortex-A53 and Cortex-A57 r213651 as r214809 : [AArch64] Use REG_P and CONST_INT_P instead of GET_CODE + comparison r213659 as r214844 : [AArch64] Prefer dup to zip for vec_perm_const; enable dup for bigendian; add testcase. r213692 as r214313 : [AArch32] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook r213701 as r214517 : Testsuiteisms. r213711 as r214514 : [AArch64] Use MOVN to generate 64-bit negative immediates where sensible r213713 as r214515 : [AArch64] Delete f_sels, f_seld types, use fcsel instead r214503 as r214845 : [AArch64] Fix typo r214526 as r214847 : PR target/60606 target/61330 fix ICE r215004 as r215069 : [AArch64] PR target/63190 This will be part of our 2014.09 4.9 release. Thanks, Yvan
