Hello,
This patch adds patterns to support FMA new insns.
Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.
Is it ok for trunk?
gcc/
* config/i386/sse.md
(define_mode_iterator VF_AVX512VL): New.
(define_mode_iterator FMAMODEM): Allow 128/256bit evex version.
(define_mode_iterator FMAMODE): Ditto.
(define_expand "avx512f_fmadd_<mode>_maskz<round_expand_name>"): Delete.
(define_expand "<avx512>_fmadd_<mode>_maskz<round_expand_name>"): New.
(define_insn
"<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>"): Delete.
(define_insn
"<sd_mask_codefor>fma_fmadd_noavx512_<mode><sd_maskz_name><round_name>":
New.
(define_insn "avx512f_fmadd_<mode>_mask<round_name>"): Delete.
(define_insn "<avx512>_fmadd_<mode>_mask<round_name>"): New.
(define_insn "avx512f_fmadd_<mode>_mask3<round_name>"): Delete.
(define_insn "<avx512>_fmadd_<mode>_mask3<round_name>"): New.
(define_insn
"<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>"): Delete.
(define_insn
"<sd_mask_codefor>fma_fmsub_noavx512<mode><sd_maskz_name><round_name>"):
New.
(define_insn
"<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>"): Use
VF_AVX512VL.
(define_insn "avx512f_fmadd_<mode>_mask<round_name>"): Delete.
(define_insn "<avx512>_fmadd_<mode>_mask<round_name>"): New.
(define_insn "avx512f_fmadd_<mode>_mask3<round_name>"): Delete.
(define_insn "<avx512>_fmadd_<mode>_mask3<round_name>"): New.
(define_insn
"<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>"): Delete.
(define_insn
"<sd_mask_codefor>fma_fmsub_noavx512<mode><sd_maskz_name><round_name>"):
New.
(define_insn "avx512f_fmsub_<mode>_mask<round_name>"): Delete.
(define_insn "<avx512>_fmsub_<mode>_mask<round_name>"): New.
(define_insn "avx512f_fmsub_<mode>_mask3<round_name>"): Delete.
(define_insn "<avx512>_fmsub_<mode>_mask3<round_name>"): New.
(define_insn
"<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>"):
Delete.
(define_insn
"<sd_mask_codefor>fma_fnmadd_noavx512_<mode><sd_maskz_name><round_name>"):
New.
(define_insn
"<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>"):
Use VF_AVX512VL.
(define_insn "avx512f_fnmadd_<mode>_mask<round_name>"): Delete.
(define_insn "<avx512>_fnmadd_<mode>_mask<round_name>"): New.
(define_insn "avx512f_fnmadd_<mode>_mask3<round_name>"): Delete.
(define_insn "<avx512>_fnmadd_<mode>_mask3<round_name>"): New.
(define_insn
"<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>"):
Delete.
(define_insn
"<sd_mask_codefor>fma_fnmsub_noavx512_<mode><sd_maskz_name><round_name>"): New.
(define_insn
"<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>"):
Use VF_AVX512VL.
(define_insn "avx512f_fnmsub_<mode>_mask<round_name>"): Delete.
(define_insn "<avx512>_fnmsub_<mode>_mask<round_name>"): New.
(define_insn "avx512f_fnmsub_<mode>_mask3<round_name>"): Delete.
(define_insn "<avx512>_fnmsub_<mode>_mask3<round_name>"): New.
(define_expand "avx512f_fmaddsub_<mode>_maskz<round_expand_name>"):
Delete.
(define_expand "<avx512>_fmaddsub_<mode>_maskz<round_expand_name>"):
New.
(define_insn
"<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>"):
Rename to
(define_insn
"<sd_mask_codefor>fma_fmaddsub_noavx512_<mode><sd_maskz_name><round_name>"):
this.
(define_insn
"<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>"):
Use VF_AVX512VL.
(define_insn "avx512f_fmaddsub_<mode>_mask<round_name>"): Delete.
(define_insn "<avx512>_fmaddsub_<mode>_mask<round_name>"): New.
(define_insn "avx512f_fmaddsub_<mode>_mask3<round_name>"): Delete.
(define_insn "<avx512>_fmaddsub_<mode>_mask3<round_name>"): New.
(define_insn
"<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>"):
Rename to
(define_insn
"<sd_mask_codefor>fma_fmsubadd_noavx512_<mode><sd_maskz_name><round_name>"):
this.
(define_insn
"<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>"):
Use VF_AVX512VL.
(define_insn "avx512f_fmsubadd_<mode>_mask<round_name>"): Delete.
(define_insn "<avx512>_fmsubadd_<mode>_mask<round_name>"): New.
(define_insn "avx512f_fmsubadd_<mode>_mask3<round_name>"): Delete.
(define_insn "<avx512>_fmsubadd_<mode>_mask3<round_name>"): New.
--
Thanks, K
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index afdca58..310c29f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -239,6 +239,10 @@
[V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
+(define_mode_iterator VF_AVX512VL
+ [V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
+ V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
+
(define_mode_iterator VF2_AVX512VL
[V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
@@ -2960,10 +2964,10 @@
(define_mode_iterator FMAMODEM
[(SF "TARGET_SSE_MATH && (TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F)")
(DF "TARGET_SSE_MATH && (TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F)")
- (V4SF "TARGET_FMA || TARGET_FMA4")
- (V2DF "TARGET_FMA || TARGET_FMA4")
- (V8SF "TARGET_FMA || TARGET_FMA4")
- (V4DF "TARGET_FMA || TARGET_FMA4")
+ (V4SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
+ (V2DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
+ (V8SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
+ (V4DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
(V16SF "TARGET_AVX512F")
(V8DF "TARGET_AVX512F")])
@@ -2997,14 +3001,14 @@
;; The builtins for intrinsics are not constrained by SSE math enabled.
(define_mode_iterator FMAMODE
- [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F")
- (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F")
- (V4SF "TARGET_FMA || TARGET_FMA4")
- (V2DF "TARGET_FMA || TARGET_FMA4")
- (V8SF "TARGET_FMA || TARGET_FMA4")
- (V4DF "TARGET_FMA || TARGET_FMA4")
- (V16SF "TARGET_AVX512F")
- (V8DF "TARGET_AVX512F")])
+ [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F")
+ (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F")
+ (V4SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
+ (V2DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
+ (V8SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
+ (V4DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL")
+ (V16SF "TARGET_AVX512F")
+ (V8DF "TARGET_AVX512F")])
(define_expand "fma4i_fmadd_<mode>"
[(set (match_operand:FMAMODE 0 "register_operand")
@@ -3013,13 +3017,13 @@
(match_operand:FMAMODE 2 "nonimmediate_operand")
(match_operand:FMAMODE 3 "nonimmediate_operand")))])
-(define_expand "avx512f_fmadd_<mode>_maskz<round_expand_name>"
- [(match_operand:VF_512 0 "register_operand")
- (match_operand:VF_512 1 "<round_expand_nimm_predicate>")
- (match_operand:VF_512 2 "<round_expand_nimm_predicate>")
- (match_operand:VF_512 3 "<round_expand_nimm_predicate>")
+(define_expand "<avx512>_fmadd_<mode>_maskz<round_expand_name>"
+ [(match_operand:VF_AVX512VL 0 "register_operand")
+ (match_operand:VF_AVX512VL 1 "<round_expand_nimm_predicate>")
+ (match_operand:VF_AVX512VL 2 "<round_expand_nimm_predicate>")
+ (match_operand:VF_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
- "TARGET_AVX512F"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
{
emit_insn (gen_fma_fmadd_<mode>_maskz_1<round_expand_name> (
operands[0], operands[1], operands[2], operands[3],
@@ -3035,7 +3039,7 @@
(V8SF "TARGET_FMA || TARGET_FMA4")
(V4DF "TARGET_FMA || TARGET_FMA4")])
-(define_insn "<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>"
+(define_insn
"<sd_mask_codefor>fma_fmadd_noavx512_<mode><sd_maskz_name><round_name>"
[(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x")
(fma:FMAMODE_NOVF512
(match_operand:FMAMODE_NOVF512 1 "<round_nimm_predicate>"
"%0,0,v,x,x")
@@ -3053,11 +3057,11 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v,v")
- (fma:VF_512
- (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>,0")))]
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v,v")
+ (fma:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
+ (match_operand:VF_AVX512VL 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
+ (match_operand:VF_AVX512VL 3 "<round_nimm_predicate>"
"v,<round_constraint>,0")))]
"<sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3,
%0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
@@ -3067,16 +3071,16 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmadd_<mode>_mask<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v")
- (vec_merge:VF_512
- (fma:VF_512
- (match_operand:VF_512 1 "register_operand" "0,0")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v")
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>"))
+(define_insn "<avx512>_fmadd_<mode>_mask<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "0,0")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>,v")
+ (match_operand:VF_AVX512VL 3 "nonimmediate_operand"
"v,<round_constraint>"))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"@
vfmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3,
%2<round_op5>}
vfmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2,
%3<round_op5>}"
@@ -3084,13 +3088,13 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmadd_<mode>_mask3<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=x")
- (vec_merge:VF_512
- (fma:VF_512
- (match_operand:VF_512 1 "register_operand" "x")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>")
- (match_operand:VF_512 3 "register_operand" "0"))
+(define_insn "<avx512>_fmadd_<mode>_mask3<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=x")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "x")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>")
+ (match_operand:VF_AVX512VL 3 "register_operand" "0"))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
"TARGET_AVX512F"
@@ -3099,7 +3103,7 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>"
+(define_insn
"<sd_mask_codefor>fma_fmsub_noavx512<mode><sd_maskz_name><round_name>"
[(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x")
(fma:FMAMODE_NOVF512
(match_operand:FMAMODE_NOVF512 1 "<round_nimm_predicate>"
"%0,0,v,x,x")
@@ -3118,12 +3122,12 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v,v")
- (fma:VF_512
- (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
- (neg:VF_512
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>,0"))))]
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v,v")
+ (fma:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
+ (match_operand:VF_AVX512VL 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "<round_nimm_predicate>"
"v,<round_constraint>,0"))))]
"<sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3,
%0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
@@ -3133,14 +3137,14 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmsub_<mode>_mask<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v")
- (vec_merge:VF_512
- (fma:VF_512
- (match_operand:VF_512 1 "register_operand" "0,0")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v")
- (neg:VF_512
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>")))
+(define_insn "<avx512>_fmsub_<mode>_mask<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "0,0")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>,v")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "nonimmediate_operand"
"v,<round_constraint>")))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
"TARGET_AVX512F"
@@ -3151,23 +3155,23 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmsub_<mode>_mask3<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v")
- (vec_merge:VF_512
- (fma:VF_512
- (match_operand:VF_512 1 "register_operand" "v")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>")
- (neg:VF_512
- (match_operand:VF_512 3 "register_operand" "0")))
+(define_insn "<avx512>_fmsub_<mode>_mask3<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "v")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "register_operand" "0")))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"vfmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1,
%2<round_op5>}"
[(set_attr "isa" "fma_avx512f")
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>"
+(define_insn
"<sd_mask_codefor>fma_fnmadd_noavx512_<mode><sd_maskz_name><round_name>"
[(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x")
(fma:FMAMODE_NOVF512
(neg:FMAMODE_NOVF512
@@ -3186,12 +3190,12 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v,v")
- (fma:VF_512
- (neg:VF_512
- (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v"))
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>,0")))]
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v,v")
+ (fma:VF_AVX512VL
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v"))
+ (match_operand:VF_AVX512VL 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
+ (match_operand:VF_AVX512VL 3 "<round_nimm_predicate>"
"v,<round_constraint>,0")))]
"<sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfnmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3,
%0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
@@ -3201,17 +3205,17 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fnmadd_<mode>_mask<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v")
- (vec_merge:VF_512
- (fma:VF_512
- (neg:VF_512
- (match_operand:VF_512 1 "register_operand" "0,0"))
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v")
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>"))
+(define_insn "<avx512>_fnmadd_<mode>_mask<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "0,0"))
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>,v")
+ (match_operand:VF_AVX512VL 3 "nonimmediate_operand"
"v,<round_constraint>"))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"@
vfnmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3,
%2<round_op5>}
vfnmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2,
%3<round_op5>}"
@@ -3219,23 +3223,23 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fnmadd_<mode>_mask3<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v")
- (vec_merge:VF_512
- (fma:VF_512
- (neg:VF_512
- (match_operand:VF_512 1 "register_operand" "v"))
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>")
- (match_operand:VF_512 3 "register_operand" "0"))
+(define_insn "<avx512>_fnmadd_<mode>_mask3<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "v"))
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>")
+ (match_operand:VF_AVX512VL 3 "register_operand" "0"))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"vfnmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1,
%2<round_op5>}"
[(set_attr "isa" "fma_avx512f")
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>"
+(define_insn
"<sd_mask_codefor>fma_fnmsub_noavx512_<mode><sd_maskz_name><round_name>"
[(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x")
(fma:FMAMODE_NOVF512
(neg:FMAMODE_NOVF512
@@ -3255,13 +3259,13 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v,v")
- (fma:VF_512
- (neg:VF_512
- (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v"))
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
- (neg:VF_512
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>,0"))))]
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v,v")
+ (fma:VF_AVX512VL
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v"))
+ (match_operand:VF_AVX512VL 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "<round_nimm_predicate>"
"v,<round_constraint>,0"))))]
"<sd_mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3,
%0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
@@ -3271,18 +3275,18 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fnmsub_<mode>_mask<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v")
- (vec_merge:VF_512
- (fma:VF_512
- (neg:VF_512
- (match_operand:VF_512 1 "register_operand" "0,0"))
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v")
- (neg:VF_512
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>")))
+(define_insn "<avx512>_fnmsub_<mode>_mask<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "0,0"))
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>,v")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "nonimmediate_operand"
"v,<round_constraint>")))
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F && <round_mode512bit_condition>"
"@
vfnmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3,
%2<round_op5>}
vfnmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2,
%3<round_op5>}"
@@ -3290,15 +3294,15 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fnmsub_<mode>_mask3<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v")
- (vec_merge:VF_512
- (fma:VF_512
- (neg:VF_512
- (match_operand:VF_512 1 "register_operand" "v"))
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>")
- (neg:VF_512
- (match_operand:VF_512 3 "register_operand" "0")))
+(define_insn "<avx512>_fnmsub_<mode>_mask3<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VF_AVX512VL
+ (fma:VF_AVX512VL
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 1 "register_operand" "v"))
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "register_operand" "0")))
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
"TARGET_AVX512F"
@@ -3327,11 +3331,11 @@
UNSPEC_FMADDSUB))]
"TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F")
-(define_expand "avx512f_fmaddsub_<mode>_maskz<round_expand_name>"
- [(match_operand:VF_512 0 "register_operand")
- (match_operand:VF_512 1 "<round_expand_nimm_predicate>")
- (match_operand:VF_512 2 "<round_expand_nimm_predicate>")
- (match_operand:VF_512 3 "<round_expand_nimm_predicate>")
+(define_expand "<avx512>_fmaddsub_<mode>_maskz<round_expand_name>"
+ [(match_operand:VF_AVX512VL 0 "register_operand")
+ (match_operand:VF_AVX512VL 1 "<round_expand_nimm_predicate>")
+ (match_operand:VF_AVX512VL 2 "<round_expand_nimm_predicate>")
+ (match_operand:VF_AVX512VL 3 "<round_expand_nimm_predicate>")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512F"
{
@@ -3341,7 +3345,7 @@
DONE;
})
-(define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>"
+(define_insn
"<sd_mask_codefor>fma_fmaddsub_noavx512_<mode><sd_maskz_name><round_name>"
[(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x")
(unspec:VF_128_256
[(match_operand:VF_128_256 1 "<round_nimm_predicate>" "%0,0,v,x,x")
@@ -3360,11 +3364,11 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v,v")
- (unspec:VF_512
- [(match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>,0")]
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v,v")
+ (unspec:VF_AVX512VL
+ [(match_operand:VF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
+ (match_operand:VF_AVX512VL 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
+ (match_operand:VF_AVX512VL 3 "<round_nimm_predicate>"
"v,<round_constraint>,0")]
UNSPEC_FMADDSUB))]
"TARGET_AVX512F && <sd_mask_mode512bit_condition> &&
<round_mode512bit_condition>"
"@
@@ -3375,13 +3379,13 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmaddsub_<mode>_mask<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v")
- (vec_merge:VF_512
- (unspec:VF_512
- [(match_operand:VF_512 1 "register_operand" "0,0")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v")
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>")]
+(define_insn "<avx512>_fmaddsub_<mode>_mask<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
+ (vec_merge:VF_AVX512VL
+ (unspec:VF_AVX512VL
+ [(match_operand:VF_AVX512VL 1 "register_operand" "0,0")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>,v")
+ (match_operand:VF_AVX512VL 3 "nonimmediate_operand"
"v,<round_constraint>")]
UNSPEC_FMADDSUB)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
@@ -3393,13 +3397,13 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmaddsub_<mode>_mask3<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v")
- (vec_merge:VF_512
- (unspec:VF_512
- [(match_operand:VF_512 1 "register_operand" "v")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>")
- (match_operand:VF_512 3 "register_operand" "0")]
+(define_insn "<avx512>_fmaddsub_<mode>_mask3<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VF_AVX512VL
+ (unspec:VF_AVX512VL
+ [(match_operand:VF_AVX512VL 1 "register_operand" "v")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>")
+ (match_operand:VF_AVX512VL 3 "register_operand" "0")]
UNSPEC_FMADDSUB)
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
@@ -3409,7 +3413,7 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>"
+(define_insn
"<sd_mask_codefor>fma_fmsubadd_noavx512_<mode><sd_maskz_name><round_name>"
[(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x")
(unspec:VF_128_256
[(match_operand:VF_128_256 1 "<round_nimm_predicate>" "%0,0,v,x,x")
@@ -3429,12 +3433,12 @@
(set_attr "mode" "<MODE>")])
(define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v,v")
- (unspec:VF_512
- [(match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
- (neg:VF_512
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>,0"))]
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v,v")
+ (unspec:VF_AVX512VL
+ [(match_operand:VF_AVX512VL 1 "<round_nimm_predicate>" "%0,0,v")
+ (match_operand:VF_AVX512VL 2 "<round_nimm_predicate>"
"<round_constraint>,v,<round_constraint>")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "<round_nimm_predicate>"
"v,<round_constraint>,0"))]
UNSPEC_FMADDSUB))]
"TARGET_AVX512F && <sd_mask_mode512bit_condition> &&
<round_mode512bit_condition>"
"@
@@ -3445,14 +3449,14 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmsubadd_<mode>_mask<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v,v")
- (vec_merge:VF_512
- (unspec:VF_512
- [(match_operand:VF_512 1 "register_operand" "0,0")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>,v")
- (neg:VF_512
- (match_operand:VF_512 3 "<round_nimm_predicate>"
"v,<round_constraint>"))]
+(define_insn "<avx512>_fmsubadd_<mode>_mask<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v,v")
+ (vec_merge:VF_AVX512VL
+ (unspec:VF_AVX512VL
+ [(match_operand:VF_AVX512VL 1 "register_operand" "0,0")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>,v")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "nonimmediate_operand"
"v,<round_constraint>"))]
UNSPEC_FMADDSUB)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
@@ -3464,14 +3468,14 @@
(set_attr "type" "ssemuladd")
(set_attr "mode" "<MODE>")])
-(define_insn "avx512f_fmsubadd_<mode>_mask3<round_name>"
- [(set (match_operand:VF_512 0 "register_operand" "=v")
- (vec_merge:VF_512
- (unspec:VF_512
- [(match_operand:VF_512 1 "register_operand" "v")
- (match_operand:VF_512 2 "<round_nimm_predicate>"
"<round_constraint>")
- (neg:VF_512
- (match_operand:VF_512 3 "register_operand" "0"))]
+(define_insn "<avx512>_fmsubadd_<mode>_mask3<round_name>"
+ [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VF_AVX512VL
+ (unspec:VF_AVX512VL
+ [(match_operand:VF_AVX512VL 1 "register_operand" "v")
+ (match_operand:VF_AVX512VL 2 "nonimmediate_operand"
"<round_constraint>")
+ (neg:VF_AVX512VL
+ (match_operand:VF_AVX512VL 3 "register_operand" "0"))]
UNSPEC_FMADDSUB)
(match_dup 3)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
