> On Aug 12, 2014, at 7:40 AM, Alan Lawrence <alan.lawre...@arm.com> wrote: > > (It is no more expensive.)
Yes on some processors it could be. Thanks, Andrew > > gcc/ChangeLog: > > * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize > SIMD reg variant. > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index > f8eb305140e7b0aed006b33f1724a90939e48316..0a8ca4bcc7941f912c8d42200b33206d4188fa48 > 100644 --- a/gcc/config/aarch64/aarch64.md +++ > b/gcc/config/aarch64/aarch64.md @@ -1188,10 +1188,10 @@ (define_insn > "*adddi3_aarch64" [(set - (match_operand:DI 0 "register_operand" > "=rk,rk,rk,!w") + (match_operand:DI 0 "register_operand" "=rk,rk,rk,w") > (plus:DI - (match_operand:DI 1 "register_operand" "%rk,rk,rk,!w") - > (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,!w")))] + (match_operand:DI > 1 "register_operand" "%rk,rk,rk,w") + (match_operand:DI 2 > "aarch64_plus_operand" "I,r,J,w")))] "" "@ add\\t%x0, %x1, %2 @@ -1662,9 > +1662,9 @@ ) (define_insn "subdi3" - [(set (match_operand:DI 0 > "register_operand" "=rk,!w") - (minus:DI (match_operand:DI 1 > "register_operand" "r,!w") - (match_operand:DI 2 "register_operand" > "r,!w")))] + [(set (match_operand:DI 0 "register_operand" "=rk,w") + > (minus:DI (match_operand:DI 1 "register_operand" "r,w") + > (match_operand:DI 2 "register_operand" "r,w")))] "" "@ sub\\t%x0, %x1, %x2
