Hi Ramana,
This is the rebased patch, there is no conflict against latest trunk.  I am 
still doing some tests.  Is it OK if tests are fine?
Also, it depends on patch at 
https://gcc.gnu.org/ml/gcc-patches/2014-04/msg01923.html, I will update that 
patch two.

Thanks,
bin

Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c        (revision 212295)
+++ gcc/config/arm/arm.c        (working copy)
@@ -1588,34 +1588,38 @@ const struct tune_params arm_slowmul_tune =
 {
   arm_slowmul_rtx_costs,
   NULL,
-  NULL,                                                /* Sched adj cost.  */
-  3,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  3,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */

Please make sure alignment is maintained with comments as today. I'm not sure why I see the following diffs in your patch since you don't really should be touching those lines, that applies to all the cost tables. I haven't called out all the places where you appear to have unrelated formatting changes in detail, but have done so in one cost table.

Please re-create a patch that doesn't have these hunks.

   ARM_PREFETCH_NOT_BENEFICIAL,
-  true,                                                /* Prefer constant 
pool.  */
+  true,                                        /* Prefer constant pool.  */

Likewise.

   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */

Likewise.

+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_fastmul_tune =
 {
   arm_fastmul_rtx_costs,
   NULL,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  true,                                                /* Prefer constant 
pool.  */
+  true,                                        /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 /* StrongARM has early execution of branches, so a sequence that is worth
@@ -1625,17 +1629,19 @@ const struct tune_params arm_strongarm_tune =
 {
   arm_fastmul_rtx_costs,
   NULL,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  3,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  3,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  true,                                                /* Prefer constant 
pool.  */
+  true,                                        /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_xscale_tune =
@@ -1643,50 +1649,56 @@ const struct tune_params arm_xscale_tune =
   arm_xscale_rtx_costs,
   NULL,
   xscale_sched_adjust_cost,
-  2,                                           /* Constant limit.  */
-  3,                                           /* Max cond insns.  */
+  2,                                   /* Constant limit.  */
+  3,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  true,                                                /* Prefer constant 
pool.  */
+  true,                                        /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_9e_tune =
 {
   arm_9e_rtx_costs,
   NULL,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  true,                                                /* Prefer constant 
pool.  */
+  true,                                        /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_v6t2_tune =
 {
   arm_9e_rtx_costs,
   NULL,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 /* Generic Cortex tuning.  Use more specific tunings if appropriate.  */
@@ -1694,34 +1706,38 @@ const struct tune_params arm_cortex_tune =
 {
   arm_9e_rtx_costs,
   &generic_extra_costs,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_cortex_a8_tune =
 {
   arm_9e_rtx_costs,
   &cortexa8_extra_costs,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer Neon for stringops.  
*/
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_cortex_a7_tune =
@@ -1729,67 +1745,75 @@ const struct tune_params arm_cortex_a7_tune =
   arm_9e_rtx_costs,
   &cortexa7_extra_costs,
   NULL,
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                   /* Vectorizer costs.  */
-  false,                                       /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer Neon for stringops.  
*/
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_cortex_a15_tune =
 {
   arm_9e_rtx_costs,
   &cortexa15_extra_costs,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  2,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  2,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  true,                                                /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  true, true                                    /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  true, true,                          /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer Neon for stringops.  
*/
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_cortex_a53_tune =
 {
   arm_9e_rtx_costs,
   &cortexa53_extra_costs,
-  NULL,                                                /* Scheduler cost 
adjustment.  */
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Scheduler cost adjustment.  
*/
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                   /* Vectorizer costs.  */
-  false,                                       /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_cortex_a57_tune =
 {
   arm_9e_rtx_costs,
   &cortexa57_extra_costs,
-  NULL,                                         /* Scheduler cost adjustment.  
*/
-  1,                                           /* Constant limit.  */
-  2,                                           /* Max cond insns.  */
+  NULL,                                        /* Scheduler cost adjustment.  
*/
+  1,                                   /* Constant limit.  */
+  2,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  true,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                /* Prefer non short circuit.  */
-  &arm_default_vec_cost,                       /* Vectorizer costs.  */
-  false,                                       /* Prefer Neon for 64-bits 
bitops.  */
-  true, true                                   /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  true, true,                          /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
@@ -1799,17 +1823,19 @@ const struct tune_params arm_cortex_a5_tune =
 {
   arm_9e_rtx_costs,
   NULL,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  1,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  1,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_cortex_a5_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {false, false},                              /* Prefer non short circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {false, false},                      /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer Neon for stringops.  
*/
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_cortex_a9_tune =
@@ -1817,16 +1843,18 @@ const struct tune_params arm_cortex_a9_tune =
   arm_9e_rtx_costs,
   &cortexa9_extra_costs,
   cortex_a9_sched_adjust_cost,
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_BENEFICIAL(4,32,32),
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_cortex_a12_tune =
@@ -1834,16 +1862,18 @@ const struct tune_params arm_cortex_a12_tune =
   arm_9e_rtx_costs,
   &cortexa12_extra_costs,
   NULL,
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_BENEFICIAL(4,32,32),
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  true,                                                /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  true,                                        /* Prefer Neon for stringops.  
*/
+  8                                    /* Maximum insns to inline memset.  */
 };

 /* armv7m tuning.  On Cortex-M4 cores for example, MOVW/MOVT take a single
@@ -1857,17 +1887,19 @@ const struct tune_params arm_v7m_tune =
 {
   arm_9e_rtx_costs,
   &v7m_extra_costs,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  2,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  2,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  true,                                                /* Prefer constant 
pool.  */
+  true,                                        /* Prefer constant pool.  */
   arm_cortex_m_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {false, false},                              /* Prefer non short circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {false, false},                      /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
@@ -1876,17 +1908,19 @@ const struct tune_params arm_v6m_tune =
 {
   arm_9e_rtx_costs,
   NULL,
-  NULL,                                                /* Sched adj cost.  */
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  NULL,                                        /* Sched adj cost.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  false,                                       /* Prefer constant pool.  */
+  false,                               /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {false, false},                              /* Prefer non short circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {false, false},                      /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };

 const struct tune_params arm_fa726te_tune =
@@ -1894,16 +1928,18 @@ const struct tune_params arm_fa726te_tune =
   arm_9e_rtx_costs,
   NULL,
   fa726te_sched_adjust_cost,
-  1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
+  1,                                   /* Constant limit.  */
+  5,                                   /* Max cond insns.  */
   ARM_PREFETCH_NOT_BENEFICIAL,
-  true,                                                /* Prefer constant 
pool.  */
+  true,                                        /* Prefer constant pool.  */
   arm_default_branch_cost,
-  false,                                       /* Prefer LDRD/STRD.  */
-  {true, true},                                        /* Prefer non short 
circuit.  */
-  &arm_default_vec_cost,                        /* Vectorizer costs.  */
-  false,                                        /* Prefer Neon for 64-bits 
bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,           /* Vectorizer costs.  */
+  false,                               /* Prefer Neon for 64-bits bitops.  */
+  false, false,                                /* Prefer 32-bit encodings.  */
+  false,                               /* Prefer Neon for stringops.  */
+  8                                    /* Maximum insns to inline memset.  */
 };





Thanks,
bin

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