Ping x2.
On 14/6/20 2:24 PM, Chung-Lin Tang wrote:
> Ping.
>
> On 2014/6/9 10:03 PM, Chung-Lin Tang wrote:
>> Hi Richard,
>> As we talked about earlier, here's a patch to add a compiler option to
>> work around Cortex-A9 MPCore errata 761319:
>> http://infocenter.arm.com/help/topic/com.arm.doc.uan0004a/UAN0004A_a9_read_read.pdf
>>
>> What the option does basically, is to scan for volatile loads during
>> reorg, and add a dmb barrier after it. It also strives to make dmb
>> conditionally executed under TARGET_THUMB2, which means a new Thumb-2
>> specific *memory_barrier_t2 pattern in sync.md, with adjusted
>> conds/predicable attributes and %? in output strings.
>>
>> Patch originally written by Julian, with additions by Meador, and
>> finally a few trivial adjustments by me. Again, we've been carrying this
>> fix for a release or two. Okay for trunk?
>>
>> Thanks,
>> Chung-Lin
>>
>> 2014-06-09 Julian Brown <jul...@codesourcery.com>
>> Meador Inge <mead...@codesourcery.com>
>> Chung-Lin Tang <clt...@codesourcery.com>
>>
>> * config/arm/arm.c (arm_option_override): Emit warning if
>> -mfix-cortex-a9-volatile-hazards is used on an incompatible CPU.
>> (any_volatile_loads_p): New.
>> (arm_cortex_a9_errata_reorg): New.
>> (arm_reorg): Call arm_cortex_a9_errata_reorg.
>> * config/arm/arm.opt (mfix-cortex-a9-volatile-hazards): Add
>> option.
>> * config/arm/sync.md (*memory_barrier): Don't use on Thumb-2.
>> (*memory_barrier_t2): New, allow conditional execution on
>> Thumb-2.
>> * doc/invoke.texi (-mfix-cortex-a9-volatile-hazards): Add
>> documentation.
>>
>> testsuite/
>> * lib/target-supports.exp (check_effective_target_arm_dmb): New.
>> * gcc.target/arm/a9-volatile-ordering-erratum-1.c: New test.
>> * gcc.target/arm/a9-volatile-ordering-erratum-2.c: New test.
>> * gcc.target/arm/a9-volatile-ordering-erratum-3.c: New test.
>> * gcc.target/arm/a9-volatile-ordering-erratum-4.c: New test.
>>
>
