Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.

[Kyrill Tkachov]

Hi James,

On 19/06/14 14:12, James Greenhalgh wrote:
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
>index 
266d7873a5a1b8dbb7f955c3f13cf370920a9c4a..7c5b5a566ebfd907b83b38eed2e214738e7e9bd4 
100644
>--- a/gcc/config/aarch64/aarch64.md
>+++ b/gcc/config/aarch64/aarch64.md
>@@ -1068,16 +1068,17 @@ (define_expand "add<mode>3"
>  
>  (define_insn "*addsi3_aarch64"
>    [(set
>-    (match_operand:SI 0 "register_operand" "=rk,rk,rk")
>+    (match_operand:SI 0 "register_operand" "=rk,rk,w,rk")
>      (plus:SI
>-     (match_operand:SI 1 "register_operand" "%rk,rk,rk")
>-     (match_operand:SI 2 "aarch64_plus_operand" "I,r,J")))]
>+     (match_operand:SI 1 "register_operand" "%rk,rk,w,rk")
>+     (match_operand:SI 2 "aarch64_plus_operand" "I,r,w,J")))]
>    ""
>    "@
>    add\\t%w0, %w1, %2
>    add\\t%w0, %w1, %w2
>+  add\\t%0.2s, %1.2s, %2.2s
>    sub\\t%w0, %w1, #%n2"
>-  [(set_attr "type" "alu_imm,alu_reg,alu_imm")]
>+  [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")]
>  )
>  
Minor nit, you should set the "simd" attribute to yes for the added 
alternative to make sure it doesn't get selected when !TARGET_SIMD

Thanks,
Kyrill