Hello,as reported in PR 61503, there seems to be a typo in the shrd pattern. I think it is quite unlikely to cause any problem, because the pattern is 1 instruction too long for combine to recognize it (by the way, if someone has suggestions for PR 55583...). But it is still better to fix it.
Bootstrap+testsuite on x86_64-linux-gnu. 2014-06-21 Marc Glisse <marc.gli...@inria.fr> PR target/61503 * config/i386/i386.md (x86_64_shrd, x86_shrd): Replace ashiftrt with lshiftrt. -- Marc Glisse
Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md (revision 211856) +++ gcc/config/i386/i386.md (working copy) @@ -9601,37 +9601,37 @@ (match_operand:<DWI> 1 "register_operand") (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] "TARGET_CMOVE" [(const_int 0)] "ix86_split_<shift_insn> (operands, operands[3], <DWI>mode); DONE;") (define_insn "x86_64_shrd" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") - (ior:DI (ashiftrt:DI (match_dup 0) + (ior:DI (lshiftrt:DI (match_dup 0) (match_operand:QI 2 "nonmemory_operand" "Jc")) (ashift:DI (match_operand:DI 1 "register_operand" "r") (minus:QI (const_int 64) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "shrd{q}\t{%s2%1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") (set_attr "mode" "DI") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "vector") (set_attr "bdver1_decode" "vector")]) (define_insn "x86_shrd" [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m") - (ior:SI (ashiftrt:SI (match_dup 0) + (ior:SI (lshiftrt:SI (match_dup 0) (match_operand:QI 2 "nonmemory_operand" "Ic")) (ashift:SI (match_operand:SI 1 "register_operand" "r") (minus:QI (const_int 32) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))] "" "shrd{l}\t{%s2%1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") (set_attr "mode" "SI") (set_attr "pent_pair" "np")