On 5 June 2014 09:29, Ramana Radhakrishnan <ramana....@googlemail.com> wrote: >> >> Thanks Richard for the comments. My primary intention here is to use >> TARGET_SPILL_CLASS to make FP_REGS as spill registers. > >> Do you think >> AArch64 can benefit from TARGET_SPILL_CLASS hook. I agree that just >> increasing GP2FP and FP2GP for all the modes as I am doing is not the >> right think to do. >> > > I suspect TARGET_SPILL_CLASS again needs to be a per-core decision, > the cost of moving between FP and Integer registers really depends on > the implementation and having this spill all the time to FP register > may not be good enough. So a default definition of TARGET_SPILL_CLASS > doesn't sound to me prima-facie. > > I don't think increasing GP2FP and FP2GP costs is a bad thing. In a > number of benchmarks we've seen increased moves between FP and integer > registers and having this fix appears to help some of them. However > moving this to generic model needs more benchmarking across a variety > of cores before it can safely be applied there.
I'm aligned with Richards earlier comment on this topic. Specifically I'd like to see numbers in processor specific tuning tables, then we can take a view on how to adjust the generic numbers. /Marcus
