Hi Richard, I've realised that I may need to do 'something' to prevent GCC from loading or storing DFmode/DImode values to/from FPRs using pairs of SWC1/LWC1 when using an unaligned address. Initial tests show that when loading from an unaligned address (4-byte aligned) then GCC loads the two halves of a 64-bit value into GPRs and then moves across to FPRs. This is good but I don't know if it is guaranteed.
From what I can tell the backend doesn't specifically deal with loading unaligned data but rather the normal load/store patterns are used by the middle end. As such I'm not sure there is anything to prevent direct loads to FPRs by parts. Do you know one way or the other if unaligned doubles can currently be loaded via pairs of lwc1 (same for store) and if so can you advise on an approach I could try to prevent this for FPXX? I will try to figure this out on my own in the meantime. Regards, Matthew
