On 22/05/14 01:08, Marcus Shawcroft wrote:
> On 15 May 2014 01:10, Kugan <kugan.vivekanandara...@linaro.org> wrote:
>>
>> Hi All,
>>
>> AAarch64 back-end defines GENERAL_REGS and CORE_REGS with the same set
>> of register. Is there any reason why we need this?
>
> Nope an artifact of the early evolution of AArch64. Long ago CORE_REGS
> did not include SP. Your patch is fine, commit it.
With these changes, Christophe has noted a regression in
aarch64_be-none-elf
(http://cbuild.validation.linaro.org/build/cross-validation/gcc/210735/report-build-info.html).
One of the reduced test case is attached. Here part of the asm changes to:
fmov d1, x20
fmov v1.d[1], x19
+ str q0, [x29, 64]
+ str x22, [x29, 64]
fmov d0, x21
- fmov v0.d[1], x22
bl __multf3
orr v1.16b, v0.16b, v0.16b
Due to the cost changes in IRA, now part of the arguments(v0.d[1]) for
multf3 ends up in stack. Reason for this us, in IRA, assign_hard_reg,
while iterating for the cost for assigning register to reg:TI 99,
allocates register 32 (FP register). Which I think is wrong. After which
LRA makes it worse. There could be a latent bug here in LRA side but I
think still we need to look at cost model as well. Increasing the cost
model like below helps here.
- NAMED_PARAM (GP2FP, 2),
- NAMED_PARAM (FP2GP, 2),
+ NAMED_PARAM (GP2FP, 3),
+ NAMED_PARAM (FP2GP, 3),
IRA Log for r99
[...]
r99: preferred GENERAL_REGS, alternative ALL_REGS, allocno ALL_REGS
a4 (r99,l0) best GENERAL_REGS, allocno ALL_REGS
[...]
a4(r99,l0) costs: GENERAL_REGS:2000,2000 POINTER_REGS:2000,2000
FP_LO_REGS:4000,4000 FP_REGS:4000,4000 ALL_REGS:8000,8000 MEM:12000,12000
[...]
;; a4(r99,l0) conflicts:
;; subobject 0: a3(r90,l0) a2(r93,l0) a5(r89,l0) a6(r88,l0)
;; total conflict hard regs: 33
;; conflict hard regs: 33
[...]
Allocno a4r99 of ALL_REGS(62) has 60 avail. regs 0-28 32 34-63,
node: 0-28 32 34-63 obj 0 (confl regs = 29 31 33 64 65), obj 1 (confl
regs = 29 31 33 64 65)
[...]
Pushing a4(r99,l0)(cost 0)
[...]
Popping a4(r99,l0) -- assign reg 32
[...]
RTL snip from IRA Log for r99
[...]
(insn 25 23 74 5 (set (reg:TF 33 v1)
(reg:TF 32 v0)) t.c:12 40 {*movtf_aarch64}
(expr_list:REG_DEAD (reg:TF 32 v0)
(nil)))
(insn 74 25 75 5 (clobber (reg:TI 99 [ d+-8 ])) t.c:12 -1
(nil))
(insn 75 74 76 5 (set (subreg:DI (reg:TI 99 [ d+-8 ]) 0)
(reg:DI 88 [ d ])) t.c:12 34 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 88 [ d ])
(nil)))
(insn 76 75 77 5 (set (subreg:DI (reg:TI 99 [ d+-8 ]) 8)
(reg:DI 89 [ d+8 ])) t.c:12 34 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 89 [ d+8 ])
(nil)))
(insn 77 76 27 5 (set (reg:TF 32 v0)
(subreg:TF (reg:TI 99 [ d+-8 ]) 0)) t.c:12 40 {*movtf_aarch64}
(expr_list:REG_DEAD (reg:TI 99 [ d+-8 ])
(nil)))
[...]
RTL snip from IRA Log for instructions that had r99
[...]
(insn 25 23 74 5 (set (reg:TF 33 v1)
(reg:TF 32 v0)) t.c:12 40 {*movtf_aarch64}
(nil))
(insn 74 25 95 5 (clobber (reg:TI 32 v0 [orig:99 d+-8 ] [99])) t.c:12 -1
(nil))
(insn 95 74 75 5 (set (mem/c:TI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S16 A128])
(reg:TI 32 v0 [orig:99 d+-8 ] [99])) t.c:12 37 {*movti_aarch64}
(nil))
(insn 75 95 96 5 (set (mem/c:DI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S8 A128])
(reg:DI 22 x22 [orig:88 d ] [88])) t.c:12 34 {*movdi_aarch64}
(nil))
(insn 96 75 76 5 (set (reg:TI 32 v0 [orig:99 d+-8 ] [99])
(mem/c:TI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S16 A128])) t.c:12 37
{*movti_aarch64}
(nil))
(insn 76 96 77 5 (set (reg:DI 32 v0 [orig:99 d ] [99])
(reg:DI 21 x21 [orig:89 d+8 ] [89])) t.c:12 34 {*movdi_aarch64}
(nil))
(insn 77 76 27 5 (set (reg:TF 32 v0)
(reg:TF 32 v0 [orig:99 d+-8 ] [99])) t.c:12 40 {*movtf_aarch64}
(nil))
[...]
Thanks,
Kugan
long double
f (d, i)
long double d;
int i;
{
long double e;
d = -d;
e = d;
if (i == 1)
d *= 2;
d -= e * d;
d -= e * d;
return d;
}
