Having fixed TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to apply only to
128-bit vectors, some --with-arch=bdver3 --with-cpu=bdver3
scan-assembler failures relating to that tuning remain, because of
different choices of instructions for 128-bit vectors from the choices
expected by the tests.
This patch fixes affected tests to allow the different instruction
choices seen in this case. Tested for x86_64-linux-gnu
(--with-arch=bdver3 --with-cpu=bdver3). OK to commit?
2014-05-07 Joseph Myers <jos...@codesourcery.com>
* gcc.target/i386/avx256-unaligned-load-2.c,
gcc.target/i386/pr49002-1.c, gcc.target/i386/pr53712.c,
gcc.target/i386/pr53907.c, gcc.target/i386/pr59539-1.c: Allow
packed-single instructions.
Index: gcc/testsuite/gcc.target/i386/pr59539-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr59539-1.c (revision 210124)
+++ gcc/testsuite/gcc.target/i386/pr59539-1.c (working copy)
@@ -13,4 +13,4 @@
return _mm_movemask_epi8 (result);
}
-/* { dg-final { scan-assembler-times "vmovdqu" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu|vmovups" 1 } } */
Index: gcc/testsuite/gcc.target/i386/pr53712.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr53712.c (revision 210124)
+++ gcc/testsuite/gcc.target/i386/pr53712.c (working copy)
@@ -10,4 +10,4 @@
return __builtin_ia32_pcmpistri128 (s1chars, s2chars, 0);
}
-/* { dg-final { scan-assembler-times "movdqu" 1 } } */
+/* { dg-final { scan-assembler-times "movdqu|movups" 1 } } */
Index: gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c (revision
210124)
+++ gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c (working copy)
@@ -11,5 +11,5 @@
}
/* { dg-final { scan-assembler-not
"(avx_loaddqu256|vmovdqu\[^\n\r]*movv32qi_internal)" } } */
-/* { dg-final { scan-assembler
"(sse2_loaddqu|vmovdqu\[^\n\r]*movv16qi_internal)" } } */
+/* { dg-final { scan-assembler
"(sse2_loaddqu|(vmovdqu|vmovups)\[^\n\r]*movv16qi_internal)" } } */
/* { dg-final { scan-assembler "vinsert.128" } } */
Index: gcc/testsuite/gcc.target/i386/pr49002-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr49002-1.c (revision 210124)
+++ gcc/testsuite/gcc.target/i386/pr49002-1.c (working copy)
@@ -13,4 +13,4 @@
/* Ensure we load into xmm, not ymm. */
/* { dg-final { scan-assembler-not "vmovapd\[\t \]*\[^,\]*,\[\t \]*%ymm" } } */
-/* { dg-final { scan-assembler "vmovapd\[\t \]*\[^,\]*,\[\t \]*%xmm" } } */
+/* { dg-final { scan-assembler "vmovap\[ds\]\[\t \]*\[^,\]*,\[\t \]*%xmm" } }
*/
Index: gcc/testsuite/gcc.target/i386/pr53907.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr53907.c (revision 210124)
+++ gcc/testsuite/gcc.target/i386/pr53907.c (working copy)
@@ -13,4 +13,4 @@
return sz;
}
-/* { dg-final { scan-assembler "movdqa" } } */
+/* { dg-final { scan-assembler "movdqa|movaps" } } */
--
Joseph S. Myers
jos...@codesourcery.com
