This then left us in the happy position of being able to delete code
but I was worried about LTO streaming as these "builtins" are
essentially streamed out in LTO object code format. However since we
make no promises about LTO compatibility across releases, that's safe
but I structured the dead code elimination as Patch 2/3.
This will be committed separately in case folks want to backport Patch
1/3 separately and want to assure their users of LTO compatibility
within a release branch (if that even works) .
<DATE> Ramana Radhakrishnan <ramana.radhakrish...@arm.com>
* config/arm/arm_neon_builtins.def (vadd, vsub): Only define
the v2sf and v4sf versions.
(vand, vorr, veor, vorn, vbic): Remove.
* config/arm/neon.md (neon_vadd, neon_vsub, neon_vadd_unspec,
neon_vsub_unspec): Adjust iterator.
(neon_vorr, neon_vand, neon_vbic, neon_veor, neon_vorn): Remove.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.commit dad8586bd8c799ad26b0c7ee6e1837b50b9ef9a3
Author: Ramana Radhakrishnan <ramana.radhakrish...@arm.com>
Date: Thu Apr 24 16:00:08 2014 +0100
Remove Dead code.
diff --git a/gcc/config/arm/arm_neon_builtins.def
b/gcc/config/arm/arm_neon_builtins.def
index a00951a..85215b5 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -18,8 +18,7 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
-VAR10 (BINOP, vadd,
- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
+VAR2 (BINOP, vadd, v2sf, v4sf),
VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
@@ -54,7 +53,7 @@ VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi,
v4si, v2di),
VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
-VAR10 (BINOP, vsub, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
+VAR2 (BINOP, vsub, v2sf, v4sf),
VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
@@ -199,14 +198,4 @@ VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
VAR9 (STORESTRUCT, vst4,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
VAR7 (STORESTRUCTLANE, vst4_lane,
- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
-VAR10 (LOGICBINOP, vand,
- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR10 (LOGICBINOP, vorr,
- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR10 (BINOP, veor,
- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR10 (LOGICBINOP, vbic,
- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
-VAR10 (LOGICBINOP, vorn,
- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index aad420c..9ac393b 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1842,9 +1842,9 @@
; good for plain vadd, vaddq.
(define_expand "neon_vadd<mode>"
- [(match_operand:VDQX 0 "s_register_operand" "=w")
- (match_operand:VDQX 1 "s_register_operand" "w")
- (match_operand:VDQX 2 "s_register_operand" "w")
+ [(match_operand:VCVTF 0 "s_register_operand" "=w")
+ (match_operand:VCVTF 1 "s_register_operand" "w")
+ (match_operand:VCVTF 2 "s_register_operand" "w")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
@@ -1869,9 +1869,9 @@
; Used for intrinsics when flag_unsafe_math_optimizations is false.
(define_insn "neon_vadd<mode>_unspec"
- [(set (match_operand:VDQX 0 "s_register_operand" "=w")
- (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
- (match_operand:VDQX 2 "s_register_operand" "w")]
+ [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
+ (match_operand:VCVTF 2 "s_register_operand" "w")]
UNSPEC_VADD))]
"TARGET_NEON"
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
@@ -2132,9 +2132,9 @@
)
(define_expand "neon_vsub<mode>"
- [(match_operand:VDQX 0 "s_register_operand" "=w")
- (match_operand:VDQX 1 "s_register_operand" "w")
- (match_operand:VDQX 2 "s_register_operand" "w")
+ [(match_operand:VCVTF 0 "s_register_operand" "=w")
+ (match_operand:VCVTF 1 "s_register_operand" "w")
+ (match_operand:VCVTF 2 "s_register_operand" "w")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
@@ -2149,9 +2149,9 @@
; Used for intrinsics when flag_unsafe_math_optimizations is false.
(define_insn "neon_vsub<mode>_unspec"
- [(set (match_operand:VDQX 0 "s_register_operand" "=w")
- (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
- (match_operand:VDQX 2 "s_register_operand" "w")]
+ [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+ (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
+ (match_operand:VCVTF 2 "s_register_operand" "w")]
UNSPEC_VSUB))]
"TARGET_NEON"
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
@@ -5357,61 +5357,6 @@
[(set_attr "type" "neon_store4_4reg<q>")]
)
-(define_expand "neon_vand<mode>"
- [(match_operand:VDQX 0 "s_register_operand" "")
- (match_operand:VDQX 1 "s_register_operand" "")
- (match_operand:VDQX 2 "neon_inv_logic_op2" "")
- (match_operand:SI 3 "immediate_operand" "")]
- "TARGET_NEON"
-{
- emit_insn (gen_and<mode>3 (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "neon_vorr<mode>"
- [(match_operand:VDQX 0 "s_register_operand" "")
- (match_operand:VDQX 1 "s_register_operand" "")
- (match_operand:VDQX 2 "neon_logic_op2" "")
- (match_operand:SI 3 "immediate_operand" "")]
- "TARGET_NEON"
-{
- emit_insn (gen_ior<mode>3 (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "neon_veor<mode>"
- [(match_operand:VDQX 0 "s_register_operand" "")
- (match_operand:VDQX 1 "s_register_operand" "")
- (match_operand:VDQX 2 "s_register_operand" "")
- (match_operand:SI 3 "immediate_operand" "")]
- "TARGET_NEON"
-{
- emit_insn (gen_xor<mode>3 (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "neon_vbic<mode>"
- [(match_operand:VDQX 0 "s_register_operand" "")
- (match_operand:VDQX 1 "s_register_operand" "")
- (match_operand:VDQX 2 "neon_logic_op2" "")
- (match_operand:SI 3 "immediate_operand" "")]
- "TARGET_NEON"
-{
- emit_insn (gen_bic<mode>3_neon (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "neon_vorn<mode>"
- [(match_operand:VDQX 0 "s_register_operand" "")
- (match_operand:VDQX 1 "s_register_operand" "")
- (match_operand:VDQX 2 "neon_inv_logic_op2" "")
- (match_operand:SI 3 "immediate_operand" "")]
- "TARGET_NEON"
-{
- emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));
- DONE;
-})
-
(define_insn "neon_vec_unpack<US>_lo_<mode>"
[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
(SE:<V_unpack> (vec_select:<V_HALF>
