There seems to be a sufficiently large consensus that volatile asms should not
be treated as full optimization barriers by the compiler. This patch is a
first step towards implementing this conclusion and aims only at addressing
the code quality regressions introduced by
http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=193802
on the 4.8 branch and mainline for volatile asms.
It introduces a new, temporary predicate really_volatile_insn_p and invokes it
from the 3 places in cse.c, cselib.c and dse.c which were touched above. But
this comes with a side effect: the "blockage" standard pattern needs to be
adjusted to always use an UNSPEC_VOLATILE. That's already the case for all
the architectures that define it, but 21 architectures (aarch64 arc avr bfin
cr16 cris epiphany h8300 m32c mcore mmix mn10300 moxie msp430 nds32 picochip
rl78 rx score v850 xtensa) don't define it and therefore need to be adjusted.
Tested on x86_64-suse-linux and by building cc1 and compiling a relevant
testcase for the 21 aforementioned architectures.
2014-03-01 Eric Botcazou <ebotca...@adacore.com>
* doc/md.texi (blockage): Do not allow volatile asms.
* rtl.def (UNSPEC_VOLATILE): Adjust description.
* rtl.h (really_volatile_insn_p): Declare.
* rtlanal.c (volatile_insn_1): New predicate copied from...
(volatile_insn_p): ...this. Call it.
(really_volatile_insn_p): New predicate.
* cse.c (cse_insn): Call really_volatile_insn_p.
* cselib.c (cselib_process_insn): Likewise.
* dse.c (scan_insn): Likewise.
* emit-rtl.c (gen_blockage): Delete.
* emit-rtl.h (gen_blockage): Likewise.
* config/aarch64/aarch64.md (UNSPECV_BLOCKAGE): New enum value.
(blockage): New insn.
* config/arc/arc.md (VUNSPEC_BLOCKAGE): New constant.
(blockage): New insn.
* config/avr/avr.md (UNSPECV_BLOCKAGE): New enum value.
(blockage): New insn.
* config/bfin/bfin.md (UNSPEC_VOLATILE_BLOCKAGE): New constant.
(blockage): New insn.
* config/cr16/cr16.md (UNSPECV_BLOCKAGE): New constant.
(blockage): New insn.
* config/cris/cris.md (CRIS_UNSPECV_BLOCKAGE): New enum value.
(blockage): New insn.
* config/epiphany/epiphany.md (UNSPECV_BLOCKAGE): New constant.
(blockage): New insn.
* config/h8300/h8300.md (UNSPEC_BLOCKAGE): New constant.
(blockage): New insn.
* config/m32c/m32c.md (UNS_BLOCKAGE): New constant.
(blockage): New insn.
* config/mcore/mcore.md (UNSPECV_BLOCKAGE, UNSPECV_CONSTANT,
UNSPECV_ALIGN, UNSPECV_TABLE): New enum values.
(blockage): New insn.
(consttable_4): Use UNSPECV_CONSTANT.
(align_4): Use UNSPECV_ALIGN.
(consttable_end): Use UNSPECV_TABLE.
* config/mmix/mmix.md (UNSPECV_BLOCKAGE, UNSPECV_SYNC,
UNSPECV_NONLOCAL): New enum values.
(blockage): New insn.
(nonlocal_goto_receiver): Use UNSPECV_NONLOCAL.
(nonlocal_goto_receiver_expanded): Likewise.
(sync_icache): Use UNSPECV_SYNC.
* config/mn10300/mn10300.md (UNSPECV_BLOCKAGE): New constant.
(blockage): New insn.
* config/moxie/moxie.md (UNSPECV_BLOCKAGE): New enum value.
(blockage): New insn.
* config/msp430/msp430.md (UNS_BLOCKAGE): New enum value.
(blockage): New insn.
* config/nds32/constants.md (UNSPEC_VOLATILE_BLOCKAGE): New enum value.
* config/nds32/nds32.md (blockage): New insn.
* config/nds32/nds32.c (nds32_valid_stack_push_pop): Return false if
the insn is of the wrong kind.
* config/picochip/picochip.md (UNSPEC_BLOCKAGE): New constant.
(blockage): New insn.
* config/rl78/rl78.md (UNS_BLOCKAGE): New constant.
(blockage): New insn.
* config/rx/rx.md (UNSPEC_BLOCKAGE): New constant.
(blockage): New insn.
* config/score/score.md (BLOCKAGE): New constant.
(blockage): New insn.
* config/v850/v850.md (UNSPECV_BLOCKAGE): New constant.
(blockage): New insn.
* config/xtensa/xtensa.md (UNSPECV_BLOCKAGE): New constant.
(blockage): New insn.
--
Eric BotcazouIndex: doc/md.texi
===================================================================
--- doc/md.texi (revision 208241)
+++ doc/md.texi (working copy)
@@ -6228,7 +6228,7 @@ the values of operands 1 and 2.
This pattern defines a pseudo insn that prevents the instruction
scheduler and other passes from moving instructions and using register
equivalences across the boundary defined by the blockage insn.
-This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
+This needs to be an UNSPEC_VOLATILE pattern.
@cindex @code{memory_barrier} instruction pattern
@item @samp{memory_barrier}
Index: rtlanal.c
===================================================================
--- rtlanal.c (revision 208241)
+++ rtlanal.c (working copy)
@@ -2136,10 +2136,11 @@ remove_node_from_expr_list (const_rtx no
/* Nonzero if X contains any volatile instructions. These are instructions
which may cause unpredictable machine state instructions, and thus no
instructions or register uses should be moved or combined across them.
- This includes only volatile asms and UNSPEC_VOLATILE instructions. */
+ This includes only UNSPEC_VOLATILE instructions and, if WITH_ASMS is
+ true, also volatile asms. */
-int
-volatile_insn_p (const_rtx x)
+static int
+volatile_insn_1 (const_rtx x, bool with_asms)
{
const RTX_CODE code = GET_CODE (x);
switch (code)
@@ -2164,7 +2165,7 @@ volatile_insn_p (const_rtx x)
case ASM_INPUT:
case ASM_OPERANDS:
- if (MEM_VOLATILE_P (x))
+ if (with_asms && MEM_VOLATILE_P (x))
return 1;
default:
@@ -2196,6 +2197,32 @@ volatile_insn_p (const_rtx x)
return 0;
}
+/* Nonzero if X contains any volatile instructions. These are instructions
+ which may cause unpredictable machine state instructions, and thus no
+ instructions or register uses should be moved or combined across them.
+ This includes only volatile asms and UNSPEC_VOLATILE instructions.
+
+ This is the historical version, now deprecated. */
+
+int
+volatile_insn_p (const_rtx x)
+{
+ return volatile_insn_1 (x, true);
+}
+
+/* Nonzero if X contains any volatile instructions. These are instructions
+ which may cause unpredictable machine state instructions, and thus no
+ instructions or register uses should be moved or combined across them.
+ This includes only UNSPEC_VOLATILE instructions.
+
+ This is the new version. */
+
+int
+really_volatile_insn_p (const_rtx x)
+{
+ return volatile_insn_1 (x, false);
+}
+
/* Nonzero if X contains any volatile memory references
UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
Index: cse.c
===================================================================
--- cse.c (revision 208241)
+++ cse.c (working copy)
@@ -5682,9 +5682,8 @@ cse_insn (rtx insn)
invalidate (XEXP (dest, 0), GET_MODE (dest));
}
- /* A volatile ASM or an UNSPEC_VOLATILE invalidates everything. */
- if (NONJUMP_INSN_P (insn)
- && volatile_insn_p (PATTERN (insn)))
+ /* A volatile instruction invalidates everything. */
+ if (NONJUMP_INSN_P (insn) && really_volatile_insn_p (PATTERN (insn)))
flush_hash_table ();
/* Don't cse over a call to setjmp; on some machines (eg VAX)
Index: rtl.def
===================================================================
--- rtl.def (revision 208241)
+++ rtl.def (working copy)
@@ -236,7 +236,9 @@ DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands
*/
DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
-/* Similar, but a volatile operation and one which may trap. */
+/* Similar, but a volatile operation and one which may trap. Moreover, it's a
+ full optimization barrier, i.e. no instructions may be moved and no register
+ (hard or pseudo) or memory equivalences may be used across it. */
DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
/* ----------------------------------------------------------------------
Index: dse.c
===================================================================
--- dse.c (revision 208241)
+++ dse.c (working copy)
@@ -2472,8 +2472,7 @@ scan_insn (bb_info_t bb_info, rtx insn)
/* Cselib clears the table for this case, so we have to essentially
do the same. */
- if (NONJUMP_INSN_P (insn)
- && volatile_insn_p (PATTERN (insn)))
+ if (NONJUMP_INSN_P (insn) && really_volatile_insn_p (PATTERN (insn)))
{
add_wild_read (bb_info);
insn_info->cannot_delete = true;
Index: emit-rtl.c
===================================================================
--- emit-rtl.c (revision 208241)
+++ emit-rtl.c (working copy)
@@ -329,21 +329,6 @@ get_reg_attrs (tree decl, int offset)
return (reg_attrs *) *slot;
}
-
-#if !HAVE_blockage
-/* Generate an empty ASM_INPUT, which is used to block attempts to schedule,
- and to block register equivalences to be seen across this insn. */
-
-rtx
-gen_blockage (void)
-{
- rtx x = gen_rtx_ASM_INPUT (VOIDmode, "");
- MEM_VOLATILE_P (x) = true;
- return x;
-}
-#endif
-
-
/* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
don't attempt to share with the various global pieces of rtl (such as
frame_pointer_rtx). */
Index: cselib.c
===================================================================
--- cselib.c (revision 208241)
+++ cselib.c (working copy)
@@ -2655,10 +2655,8 @@ cselib_process_insn (rtx insn)
/* Forget everything at a CODE_LABEL, a volatile insn, or a setjmp. */
if ((LABEL_P (insn)
- || (CALL_P (insn)
- && find_reg_note (insn, REG_SETJMP, NULL))
- || (NONJUMP_INSN_P (insn)
- && volatile_insn_p (PATTERN (insn))))
+ || (CALL_P (insn) && find_reg_note (insn, REG_SETJMP, NULL))
+ || (NONJUMP_INSN_P (insn) && really_volatile_insn_p (PATTERN (insn))))
&& !cselib_preserve_constants)
{
cselib_reset_table (next_uid);
Index: emit-rtl.h
===================================================================
--- emit-rtl.h (revision 208241)
+++ emit-rtl.h (working copy)
@@ -57,7 +57,6 @@ extern rtx replace_equiv_address (rtx, r
/* Likewise, but the reference is not required to be valid. */
extern rtx replace_equiv_address_nv (rtx, rtx);
-extern rtx gen_blockage (void);
extern rtvec gen_rtvec (int, ...);
extern rtx copy_insn_1 (rtx);
extern rtx copy_insn (rtx);
Index: rtl.h
===================================================================
--- rtl.h (revision 208241)
+++ rtl.h (working copy)
@@ -2064,6 +2064,7 @@ extern void remove_reg_equal_equiv_notes
extern int side_effects_p (const_rtx);
extern int volatile_refs_p (const_rtx);
extern int volatile_insn_p (const_rtx);
+extern int really_volatile_insn_p (const_rtx x);
extern int may_trap_p_1 (const_rtx, unsigned);
extern int may_trap_p (const_rtx);
extern int may_trap_or_fault_p (const_rtx);
Index: config/m32c/m32c.md
===================================================================
--- config/m32c/m32c.md (revision 208241)
+++ config/m32c/m32c.md (working copy)
@@ -37,7 +37,8 @@ (define_constants
])
(define_constants
- [(UNS_PROLOGUE_END 1)
+ [(UNS_BLOCKAGE 0)
+ (UNS_PROLOGUE_END 1)
(UNS_EPILOGUE_START 2)
(UNS_EH_EPILOGUE 3)
(UNS_PUSHM 4)
@@ -64,6 +65,13 @@ (define_mode_attr bwl [(QI "b") (HI "w")
(define_code_iterator eqne_cond [eq ne])
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNS_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "flags" "n")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/rx/rx.md
===================================================================
--- config/rx/rx.md (revision 208241)
+++ config/rx/rx.md (working copy)
@@ -75,6 +75,8 @@ (define_constants
(UNSPEC_BUILTIN_WAIT 51)
(UNSPEC_PID_ADDR 52)
+
+ (UNSPEC_BLOCKAGE 53)
]
)
@@ -2607,7 +2609,13 @@ (define_insn "mvfcp"
;;---------- Misc ------------------------
-;; Required by cfglayout.c...
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/avr/avr.md
===================================================================
--- config/avr/avr.md (revision 208241)
+++ config/avr/avr.md (working copy)
@@ -83,6 +83,7 @@ (define_c_enum "unspecv"
UNSPECV_SLEEP
UNSPECV_WDR
UNSPECV_DELAY_CYCLES
+ UNSPECV_BLOCKAGE
])
@@ -4876,6 +4877,13 @@ (define_insn "call_value_insn"
(set_attr "length" "1,*,1,*")
(set_attr "adjust_len" "*,call,*,call")])
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/nds32/nds32.md
===================================================================
--- config/nds32/nds32.md (revision 208241)
+++ config/nds32/nds32.md (working copy)
@@ -1993,6 +1993,13 @@ (define_expand "epilogue" [(const_int 0)
;; nop instruction.
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/nds32/nds32.c
===================================================================
--- config/nds32/nds32.c (revision 208241)
+++ config/nds32/nds32.c (working copy)
@@ -4322,6 +4322,8 @@ nds32_valid_stack_push_pop (rtx op, bool
elt = XVECEXP (op, 0, 0);
/* Pick up register element. */
elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
+ if (!REG_P (elt_reg))
+ return false;
first_regno = REGNO (elt_reg);
/* The 'push' operation is a kind of store operation.
Index: config/nds32/constants.md
===================================================================
--- config/nds32/constants.md (revision 208241)
+++ config/nds32/constants.md (working copy)
@@ -41,6 +41,7 @@ (define_c_enum "unspec_volatile_element"
UNSPEC_VOLATILE_MTUSR
UNSPEC_VOLATILE_SETGIE_EN
UNSPEC_VOLATILE_SETGIE_DIS
+ UNSPEC_VOLATILE_BLOCKAGE
])
;; ------------------------------------------------------------------------
Index: config/xtensa/xtensa.md
===================================================================
--- config/xtensa/xtensa.md (revision 208241)
+++ config/xtensa/xtensa.md (working copy)
@@ -36,6 +36,7 @@ (define_constants [
(UNSPEC_TP 10)
(UNSPEC_MEMW 11)
+ (UNSPECV_BLOCKAGE 0)
(UNSPECV_SET_FP 1)
(UNSPECV_ENTRY 2)
(UNSPECV_S32RI 4)
@@ -1614,6 +1615,13 @@ (define_expand "epilogue"
DONE;
})
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/epiphany/epiphany.md
===================================================================
--- config/epiphany/epiphany.md (revision 208241)
+++ config/epiphany/epiphany.md (working copy)
@@ -52,7 +52,8 @@ (define_constants
(UNSPEC_FP_MODE 1)
(UNSPECV_GID 0)
- (UNSPECV_GIE 1)])
+ (UNSPECV_GIE 1)
+ (UNSPECV_BLOCKAGE 2)])
;; Insn type. Used to default other attribute values.
@@ -2805,6 +2806,14 @@ (define_expand "movmisalign<mode>"
DONE;
})
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")
+ (set_attr "type" "flow")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/moxie/moxie.md
===================================================================
--- config/moxie/moxie.md (revision 208241)
+++ config/moxie/moxie.md (working copy)
@@ -18,6 +18,9 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+(define_c_enum "unspecv"
+ [UNSPECV_BLOCKAGE])
+
;; -------------------------------------------------------------------------
;; Moxie specific constraints, predicates and attributes
;; -------------------------------------------------------------------------
@@ -32,6 +35,13 @@ (define_attr "length" "" (const_int 2))
;; nop instruction
;; -------------------------------------------------------------------------
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/cris/cris.md
===================================================================
--- config/cris/cris.md (revision 208241)
+++ config/cris/cris.md (working copy)
@@ -94,6 +94,9 @@ (define_c_enum ""
;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1...
CRIS_UNSPEC_SWAP_BITS
+
+ ;; Blockage
+ CRIS_UNSPECV_BLOCKAGE
])
;; Register numbers.
@@ -3816,6 +3819,14 @@ (define_insn "*expanded_call_value_v32"
[(set_attr "cc" "clobber")
(set_attr "slottable" "has_call_slot")])
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] CRIS_UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "cc" "none")
+ (set_attr "length" "0")]
+)
+
;; Used in debugging. No use for the direct pattern; unfilled
;; delayed-branches are taken care of by other means.
Index: config/mn10300/mn10300.md
===================================================================
--- config/mn10300/mn10300.md (revision 208241)
+++ config/mn10300/mn10300.md (working copy)
@@ -42,6 +42,8 @@ (define_constants [
(UNSPEC_LIW 8)
;; This is for the low overhead loop instructions.
(UNSPEC_SETLB 9)
+
+ (UNSPECV_BLOCKAGE 0)
])
(include "predicates.md")
@@ -1678,6 +1680,12 @@ (define_expand "untyped_call"
DONE;
})
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/aarch64/aarch64.md
===================================================================
--- config/aarch64/aarch64.md (revision 208241)
+++ config/aarch64/aarch64.md (working copy)
@@ -106,6 +106,7 @@ (define_c_enum "unspec" [
(define_c_enum "unspecv" [
UNSPECV_EH_RETURN ; Represent EH_RETURN
+ UNSPECV_BLOCKAGE ; Represent 'blockage' insn
]
)
@@ -286,6 +287,14 @@ (define_insn "casesi_dispatch"
(set_attr "type" "branch")]
)
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")
+ (set_attr "type" "no_insn")]
+)
+
(define_insn "nop"
[(unspec[(const_int 0)] UNSPEC_NOP)]
""
Index: config/picochip/picochip.md
===================================================================
--- config/picochip/picochip.md (revision 208241)
+++ config/picochip/picochip.md (working copy)
@@ -111,6 +111,9 @@ (define_constants
; Internal TSTPORT instruction, used to generate a single TSTPORT
; instruction for use in the testport branch split.
(UNSPEC_INTERNAL_TESTPORT 19)
+
+ ; Blockage instruction
+ (UNSPEC_BLOCKAGE 20)
]
)
@@ -926,6 +929,12 @@ (define_expand "movmemhi"
;; NOP
;;===========================================================================
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
;; No-operation (NOP)
(define_insn "nop"
[(const_int 0)]
Index: config/arc/arc.md
===================================================================
--- config/arc/arc.md (revision 208241)
+++ config/arc/arc.md (working copy)
@@ -124,6 +124,7 @@ (define_constants
(VUNSPEC_SR 26) ; blockage insn for writing to an auxiliary register
(VUNSPEC_TRAP_S 27) ; blockage insn for trap_s generation
(VUNSPEC_UNIMP_S 28) ; blockage insn for unimp_s generation
+ (VUNSPEC_BLOCKAGE 29); blockage insn
(R0_REG 0)
(R1_REG 1)
@@ -3871,6 +3872,13 @@ (define_insn "call_value_prof"
(set_attr "predicable" "yes,yes")
(set_attr "length" "4,8")])
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")
+ (set_attr "type" "misc")])
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/mcore/mcore.md
===================================================================
--- config/mcore/mcore.md (revision 208241)
+++ config/mcore/mcore.md (working copy)
@@ -22,6 +22,14 @@
+(define_c_enum "unspecv" [
+ UNSPECV_BLOCKAGE
+ UNSPECV_CONSTANT
+ UNSPECV_ALIGN
+ UNSPECV_TABLE
+ ]
+)
+
;; -------------------------------------------------------------------------
;; Attributes
;; -------------------------------------------------------------------------
@@ -1583,6 +1591,13 @@ (define_insn "call_value_struct"
;; Misc insns
;; ------------------------------------------------------------------------
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
@@ -2924,7 +2939,7 @@ (define_peephole
;;; 4 byte integer in line.
(define_insn "consttable_4"
- [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 0)]
+ [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] UNSPECV_CONSTANT)]
""
"*
{
@@ -2936,14 +2951,14 @@ (define_insn "consttable_4"
;;; align to a four byte boundary.
(define_insn "align_4"
- [(unspec_volatile [(const_int 0)] 1)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_ALIGN)]
""
".align 2")
;;; Handle extra constant pool entries created during final pass.
(define_insn "consttable_end"
- [(unspec_volatile [(const_int 0)] 2)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_TABLE)]
""
"* return mcore_output_jump_label_table ();")
Index: config/score/score.md
===================================================================
--- config/score/score.md (revision 208241)
+++ config/score/score.md (working copy)
@@ -68,7 +68,9 @@ (define_constants
(LCW 8)
(LCE 9)
- (SFFS 10)])
+ (SFFS 10)
+
+ (BLOCKAGE 11)])
(define_attr "type"
"unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr"
@@ -1595,6 +1597,13 @@ (define_insn "return_internal_score7"
"(TARGET_SCORE7 || TARGET_SCORE7D)"
"br%S0\t%0")
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/msp430/msp430.md
===================================================================
--- config/msp430/msp430.md (revision 208241)
+++ config/msp430/msp430.md (working copy)
@@ -38,7 +38,7 @@ (define_c_enum "unspec"
UNS_GROW_AND_SWAP
UNS_SWAP_AND_SHRINK
-
+
UNS_DINT
UNS_EINT
UNS_PUSH_INTR
@@ -47,6 +47,8 @@ (define_c_enum "unspec"
UNS_BIS_SR
UNS_REFSYM_NEED_EXIT
+
+ UNS_BLOCKAGE
])
(include "predicates.md")
@@ -1254,6 +1256,12 @@ (define_insn "*bitbranch<mode>4_z"
;;------------------------------------------------------------
;; Misc
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNS_BLOCKAGE)]
+ ""
+ ""
+)
+
(define_insn "nop"
[(const_int 0)]
"1"
Index: config/rl78/rl78.md
===================================================================
--- config/rl78/rl78.md (revision 208241)
+++ config/rl78/rl78.md (working copy)
@@ -51,8 +51,15 @@ (define_constants
(UNS_TRAMPOLINE_UNINIT 21)
(UNS_NONLOCAL_GOTO 22)
+ (UNS_BLOCKAGE 23)
])
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNS_BLOCKAGE)]
+ ""
+ ""
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/h8300/h8300.md
===================================================================
--- config/h8300/h8300.md (revision 208241)
+++ config/h8300/h8300.md (working copy)
@@ -48,7 +48,8 @@
(define_constants
[(UNSPEC_INCDEC 0)
- (UNSPEC_MONITOR 1)])
+ (UNSPEC_MONITOR 1)
+ (UNSPEC_BLOCKAGE 2)])
(define_constants
[(UNSPEC_MOVMD 100)
@@ -2533,6 +2534,14 @@ (define_insn "call_value"
(const_int 2)
(const_int 4)))])
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "cc" "none")
+ (set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/v850/v850.md
===================================================================
--- config/v850/v850.md (revision 208241)
+++ config/v850/v850.md (working copy)
@@ -44,6 +44,7 @@ (define_constants
(CC_REGNUM 32) ; Condition code pseudo register
(FCC_REGNUM 33) ; Floating Condition code pseudo register
(UNSPEC_LOOP 200) ; loop counter
+ (UNSPECV_BLOCKAGE 201) ; blockage
]
)
@@ -1824,6 +1825,13 @@ (define_insn "call_value_internal_long"
(set_attr "cc" "clobber,clobber")]
)
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")
+ (set_attr "cc" "none")])
+
(define_insn "nop"
[(const_int 0)]
""
Index: config/mmix/mmix.md
===================================================================
--- config/mmix/mmix.md (revision 208241)
+++ config/mmix/mmix.md (working copy)
@@ -24,11 +24,13 @@
;; See file "rtl.def" for documentation on define_insn, match_*, et al.
;; Uses of UNSPEC in this file:
-;; UNSPEC_VOLATILE:
-;;
-;; 0 sync_icache (sync icache before trampoline jump)
-;; 1 nonlocal_goto_receiver
-;;
+
+(define_c_enum "unspecv" [
+ UNSPECV_BLOCKAGE ;; blockage
+ UNSPECV_SYNC ;; sync_icache (sync icache before trampoline jump
+ UNSPECV_NONLOCAL ;; nonlocal_goto_receiver
+ ]
+)
;; The order of insns is as in Node: Standard Names, with smaller modes
;; before bigger modes.
@@ -1088,6 +1090,12 @@ (define_expand "epilogue"
""
"mmix_expand_epilogue ();")
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+)
+
(define_insn "nop"
[(const_int 0)]
""
@@ -1119,7 +1127,7 @@ (define_insn "tablejump"
;; of "pop 0,0" until rO equals the saved value. (If it goes lower, we
;; should die with a trap.)
(define_expand "nonlocal_goto_receiver"
- [(parallel [(unspec_volatile [(match_dup 1)] 1)
+ [(parallel [(unspec_volatile [(match_dup 1)] UNSPECV_NONLOCAL)
(clobber (scratch:DI))
(clobber (reg:DI MMIX_rJ_REGNUM))])
(set (reg:DI MMIX_rJ_REGNUM) (match_dup 0))]
@@ -1146,7 +1154,7 @@ (define_expand "nonlocal_goto_receiver"
;; address and re-use them after the register stack unwind, so it's best
;; to form the address ourselves.
(define_insn "*nonlocal_goto_receiver_expanded"
- [(unspec_volatile [(match_operand:DI 1 "frame_pointer_operand" "Yf")] 1)
+ [(unspec_volatile [(match_operand:DI 1 "frame_pointer_operand" "Yf")] UNSPECV_NONLOCAL)
(clobber (match_scratch:DI 0 "=&r"))
(clobber (reg:DI MMIX_rJ_REGNUM))]
""
@@ -1233,7 +1241,7 @@ (define_insn "*nxor"
(define_insn "sync_icache"
[(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")
- (match_operand:DI 1 "const_int_operand" "I")] 0)]
+ (match_operand:DI 1 "const_int_operand" "I")] UNSPECV_SYNC)]
""
"SYNCID %1,%0")
Index: config/cr16/cr16.md
===================================================================
--- config/cr16/cr16.md (revision 208241)
+++ config/cr16/cr16.md (working copy)
@@ -40,6 +40,12 @@ (define_constants
]
)
+;; UNSPEC_VOLATILE usage
+(define_constants
+ [(UNSPECV_BLOCKAGE 0)
+ ]
+)
+
;; Attributes
(define_attr "length" "" (const_int 2))
@@ -1053,6 +1059,12 @@ (define_insn "cr16_call_value_insn_jump"
[(set_attr "length" "2")]
)
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
;; Nop
(define_insn "nop"
Index: config/bfin/bfin.md
===================================================================
--- config/bfin/bfin.md (revision 208241)
+++ config/bfin/bfin.md (working copy)
@@ -147,7 +147,8 @@ (define_constants
(UNSPEC_VOLATILE_LOAD_FUNCDESC 3)
(UNSPEC_VOLATILE_STORE_EH_HANDLER 4)
(UNSPEC_VOLATILE_DUMMY 5)
- (UNSPEC_VOLATILE_STALL 6)])
+ (UNSPEC_VOLATILE_STALL 6)
+ (UNSPEC_VOLATILE_BLOCKAGE 7)])
(define_constants
[(MACFLAG_NONE 0)
@@ -2555,6 +2556,13 @@ (define_expand "cstoresi4"
DONE;
})
+(define_insn "blockage"
+ [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_BLOCKAGE)]
+ ""
+ ""
+ [(set_attr "length" "0")]
+)
+
(define_insn "nop"
[(const_int 0)]
""
