Without aligning the asan stack base,base will only 64-bit aligned in ARM machines. But asan require 256-bit aligned base because of this: 1.right shift take ASAN_SHADOW_SHIFT(which is 3) bits are zeros 2.store multiple/load multiple instructions require the other 2 bits are zeros
that add up lowest 5 bits should be zeros.That means 32 bytes or 256 bits aligned. * asan.c (asan_emit_stack_protection): Forcing the base to align to 256 bits * cfgexpand.c (expand_used_vars): Leaving a space in the stack frame for alignment Signed-off-by: lin zuojian <manjian2...@gmail.com> --- gcc/asan.c | 6 ++++++ gcc/cfgexpand.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/gcc/asan.c b/gcc/asan.c index 53992a8..455e484 100644 --- a/gcc/asan.c +++ b/gcc/asan.c @@ -1019,6 +1019,12 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, } if (use_after_return_class == -1 && pbase) emit_move_insn (pbase, base); + + /* align base */ + base = expand_binop (Pmode, and_optab, base, + gen_int_mode (-ASAN_RED_ZONE_SIZE, Pmode), + NULL_RTX, 1, OPTAB_DIRECT); + base = expand_binop (Pmode, add_optab, base, gen_int_mode (base_offset - base_align_bias, Pmode), NULL_RTX, 1, OPTAB_DIRECT); diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index 06d494c..9e887f7 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -1843,6 +1843,8 @@ expand_used_vars (void) = alloc_stack_frame_space (redzonesz, ASAN_RED_ZONE_SIZE); data.asan_vec.safe_push (prev_offset); data.asan_vec.safe_push (offset); + /* leave a space for alignment */ + alloc_stack_frame_space (ASAN_RED_ZONE_SIZE, 1); var_end_seq = asan_emit_stack_protection (virtual_stack_vars_rtx, -- 1.8.3.2
