Hi all,
This is a simple patch which adds a space between base register and
offset during the address asm translation, making the output assembler
code format consistent for aarch64 target.
Is it Okay for stage-1?
Kind regards,
Renlin Li
gcc/ChangeLog:
2014-02-12 Renlin Li <renlin...@arm.com>
* config/aarch64/aarch64.c (aarch64_print_operand_address): Adjust
the output asm format
by adding a space between base register and offset.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index d3c5cbc..50ecdd8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3830,34 +3830,34 @@ aarch64_print_operand_address (FILE *f, rtx x)
if (addr.offset == const0_rtx)
asm_fprintf (f, "[%s]", reg_names [REGNO (addr.base)]);
else
- asm_fprintf (f, "[%s,%wd]", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, %wd]", reg_names [REGNO (addr.base)],
INTVAL (addr.offset));
return;
case ADDRESS_REG_REG:
if (addr.shift == 0)
- asm_fprintf (f, "[%s,%s]", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, %s]", reg_names [REGNO (addr.base)],
reg_names [REGNO (addr.offset)]);
else
- asm_fprintf (f, "[%s,%s,lsl %u]", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, %s, lsl %u]", reg_names [REGNO (addr.base)],
reg_names [REGNO (addr.offset)], addr.shift);
return;
case ADDRESS_REG_UXTW:
if (addr.shift == 0)
- asm_fprintf (f, "[%s,w%d,uxtw]", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, w%d, uxtw]", reg_names [REGNO (addr.base)],
REGNO (addr.offset) - R0_REGNUM);
else
- asm_fprintf (f, "[%s,w%d,uxtw %u]", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, w%d, uxtw %u]", reg_names [REGNO (addr.base)],
REGNO (addr.offset) - R0_REGNUM, addr.shift);
return;
case ADDRESS_REG_SXTW:
if (addr.shift == 0)
- asm_fprintf (f, "[%s,w%d,sxtw]", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, w%d, sxtw]", reg_names [REGNO (addr.base)],
REGNO (addr.offset) - R0_REGNUM);
else
- asm_fprintf (f, "[%s,w%d,sxtw %u]", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, w%d, sxtw %u]", reg_names [REGNO (addr.base)],
REGNO (addr.offset) - R0_REGNUM, addr.shift);
return;
@@ -3865,27 +3865,27 @@ aarch64_print_operand_address (FILE *f, rtx x)
switch (GET_CODE (x))
{
case PRE_INC:
- asm_fprintf (f, "[%s,%d]!", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, %d]!", reg_names [REGNO (addr.base)],
GET_MODE_SIZE (aarch64_memory_reference_mode));
return;
case POST_INC:
- asm_fprintf (f, "[%s],%d", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s], %d", reg_names [REGNO (addr.base)],
GET_MODE_SIZE (aarch64_memory_reference_mode));
return;
case PRE_DEC:
- asm_fprintf (f, "[%s,-%d]!", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, -%d]!", reg_names [REGNO (addr.base)],
GET_MODE_SIZE (aarch64_memory_reference_mode));
return;
case POST_DEC:
- asm_fprintf (f, "[%s],-%d", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s], -%d", reg_names [REGNO (addr.base)],
GET_MODE_SIZE (aarch64_memory_reference_mode));
return;
case PRE_MODIFY:
- asm_fprintf (f, "[%s,%wd]!", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s, %wd]!", reg_names [REGNO (addr.base)],
INTVAL (addr.offset));
return;
case POST_MODIFY:
- asm_fprintf (f, "[%s],%wd", reg_names [REGNO (addr.base)],
+ asm_fprintf (f, "[%s], %wd", reg_names [REGNO (addr.base)],
INTVAL (addr.offset));
return;
default:
@@ -3894,7 +3894,7 @@ aarch64_print_operand_address (FILE *f, rtx x)
break;
case ADDRESS_LO_SUM:
- asm_fprintf (f, "[%s,#:lo12:", reg_names [REGNO (addr.base)]);
+ asm_fprintf (f, "[%s, #:lo12:", reg_names [REGNO (addr.base)]);
output_addr_const (f, addr.offset);
asm_fprintf (f, "]");
return;
