This patch fixes PR target/60137 that shows up when some vector types get
allocated to GPR registers, and there wasn't a splitter for the type. It shows
up when targetting ISA 2.07 (power8) when VSX is disabled but Altivec (VMX) is
enabled, though I suspect there are other failure cases.
I bootstrapped and checked the patch, and it caused no regressions in the test
suite. Is it ok to apply?
[gcc]
2014-02-10 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/60137
* config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter
for VSX/Altivec vectors that land in GPR registers.
[gcc/testsuite]
2014-02-10 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/60137
* gcc.target/powerpc/pr60137.c: New file.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 207668)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -9963,6 +9963,15 @@ (define_insn_and_split "reload_vsx_from_
[(set_attr "length" "12")
(set_attr "type" "three")])
+(define_split
+ [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
+ (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
+ "reload_completed
+ && (int_reg_operand (operands[0], <MODE>mode)
+ || int_reg_operand (operands[1], <MODE>mode))"
+ [(pc)]
+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+
;; Move SFmode to a VSX from a GPR register. Because scalar floating point
;; type is stored internally as double precision in the VSX registers, we have
;; to convert it from the vector format.
Index: gcc/testsuite/gcc.target/powerpc/pr60137.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr60137.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr60137.c (revision 0)
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */
+
+/* target/60137, compiler got a 'could not split insn error'. */
+
+extern int target_flags;
+extern char fixed_regs[53];
+extern char call_used_regs[53];
+
+void init_reg_sets_1(void)
+{
+ int i;
+ for (i = 0; i < 53; i++)
+ fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags &
0x02000000) ? 2 : 1)) != 0;
+}
