On 14/01/14 09:06, Zhenqiang Chen wrote: > Hi, > > The patch fixes two IT issues: > 1) IT block is splitted for A15 (and Cortex-M). > > For A15 tune, max cond insns (max_insns_skipped) is 2, which is set as the > maximum allowed insns in an IT block (see thumb2_final_prescan_insn). So IT > which has 3 or 4 instructions, will be splitted. Take the first if-then-else > in the test case of the patch as example, it will generate ITs like: > cmp r0, #10 > ite gt > subgt r0, r0, r1 > suble r0, r1, r0 > ite gt > addgt r0, r0, #10 > suble r0, r0, #7 > It does not make sense to split the IT. For cortex-m, the IT can not be > folded if the previous insn is 4 BYTES. > > 2) For arm_v7m_tune, max cond insns is not aligned with its branch cost. In > ifcvt.c, the relation between MAX_CONDITIONAL_EXECUTE (max cond insns) and > branch cost is: > > #ifndef MAX_CONDITIONAL_EXECUTE > #define MAX_CONDITIONAL_EXECUTE \ > (BRANCH_COST (optimize_function_for_speed_p (cfun), false) \ > + 1) > #endif > > So the best value of max cond insns for v7m_tune should be 2. > > Bootstrap and no make check regression on ARM Chrome book. No make check > regression for Cortex-M3. > > Cortex-M4 O2 performance changes on coremark, dhrystone and eembc-v1: > coremark: -0.11% > dhrystone: 1.26%. > a2time01_lite: 2.63% > canrdr01_lite: 4.27% > iirflt01_lite: 6.51% > rspeed01_lite: 6.51% > dither01_lite: 7.36% > > The biggest regression in eembc-v1 is pntrch01_lite: -0.51% > All other regressions < 0.1% > > Cortex-M4 O3 performance changes are similar with O2, except one regression > due to loop alignment change. > > OK for trunk? > > Thanks! > -Zhenqiang > > 2014-01-14 Zhenqiang Chen <zhenqiang.c...@arm.com> > > * config/arm/arm.c (arm_v7m_tune): Set max_insns_skipped to 2. > (thumb2_final_prescan_insn): Set max to MAX_INSN_PER_IT_BLOCK. > > testsuite/ChangeLog: > 2014-01-14 Zhenqiang Chen <zhenqiang.c...@arm.com> > > * gcc.target/arm/its.c: New test. >
OK. R.
