Hi,
This patch and the preceding aarch64.md patches all look good to me, but
I cannot approve it.
Thanks for adding the support for these missing patterns and defines!
Yufeng
On 01/08/14 18:13, Richard Henderson wrote:
We have good support for TImode arithmetic, so no need to do anything
with inline assembly.
include/
* longlong.h [__aarch64__] (add_ssaaaa, sub_ddmmss, umul_ppmm): New.
[__aarch64__] (COUNT_LEADING_ZEROS_0): Define in terms of W_TYPE_SIZE.
---
include/longlong.h | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/include/longlong.h b/include/longlong.h
index b4c1f400..1b11fc7 100644
--- a/include/longlong.h
+++ b/include/longlong.h
@@ -123,19 +123,35 @@ extern const UQItype __clz_tab[256] attribute_hidden;
#endif /* __GNUC__< 2 */
#if defined (__aarch64__)
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+ do { \
+ UDWtype __x = (UDWtype)(UWtype)(ah)<< 64 | (UWtype)(al); \
+ __x += (UDWtype)(UWtype)(bh)<< 64 | (UWtype)(bl); \
+ (sh) = __x>> W_TYPE_SIZE; \
+ (sl) = __x;
\
+ } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+ do { \
+ UDWtype __x = (UDWtype)(UWtype)(ah)<< 64 | (UWtype)(al); \
+ __x -= (UDWtype)(UWtype)(bh)<< 64 | (UWtype)(bl); \
+ (sh) = __x>> W_TYPE_SIZE; \
+ (sl) = __x;
\
+ } while (0)
+#define umul_ppmm(ph, pl, m0, m1) \
+ do { \
+ UDWtype __x = (UDWtype)(UWtype)(m0) * (UWtype)(m1);
\
+ (ph) = __x>> W_TYPE_SIZE; \
+ (pl) = __x;
\
+ } while (0)
+#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
#if W_TYPE_SIZE == 32
#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
-#define COUNT_LEADING_ZEROS_0 32
-#endif /* W_TYPE_SIZE == 32 */
-
-#if W_TYPE_SIZE == 64
+#elif W_TYPE_SIZE == 64
#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clzll (X))
#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctzll (X))
-#define COUNT_LEADING_ZEROS_0 64
#endif /* W_TYPE_SIZE == 64 */
-
#endif /* __aarch64__ */
#if defined (__alpha)&& W_TYPE_SIZE == 64
