On Fri, Dec 20, 2013 at 5:47 PM, Ilya Tocar <tocarip.in...@gmail.com> wrote: >> > Perhaps we should add sandybridge, ivybridge and haswell aliases for >> > corei7-avx, core-avx-i, core-avx2? I mean, it is a nightmare to remember >> > which one has the i7 in and which doesn't even for me. >> >> Yes please, I think this is a good idea. > > I've added aliases for haswell, sandybridge, ivybridge, bonnell, > nehalem and silvermont. > >>BTW, I wonder if we add a bunch of new names to the table it isn't a right >>time to also introduce macros for some common PTA_* flag combinations, > > IMO full list of PTA_* helps quickly identify what is supported. > > 2013-12-20 Tocar Ilya <ilya.to...@intel.com> > > * config/i386/i386.c (ix86_option_override_internal): Add > haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont. > * doc/invoke.texi: Document them.
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index dcc1893..365ddbf 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -14645,19 +14645,41 @@ SSE2 and SSE3 instruction set support. > Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 > instruction set support. > > +@item nehalem > +Same as corei7. > +Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, > +SSE4.1, SSE4.2 and POPCNT instruction set support. > + > @item corei7 > Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, > SSE4.1, SSE4.2 and POPCNT instruction set support. If these are the same, will it work to just add new @item under existing one, like: @item corei7 +@item nehalem Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and POPCNT instruction set support. Uros.
