Hello,
The attached patch deprecates the SH options mcbranchdi and mcmpeqdi,
since they turn out to be not so useful.
For example, disabling the cbranchdi pattern results in worse code for
-Os than -O1 and enabling the cmpeqdi patterns seems to trigger
broken/incomplete code paths. Effectively this is a fix for PR 51697.
Tested with
make info dvi pdf
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
and no new failures.
Committed as revision 205794.
Cheers,
Oleg
gcc/ChangeLog:
PR target/52898
PR target/51697
* common/config/sh/sh-common.c (sh_option_optimization_table): Remove
OPT_mcbranchdi entry.
* config/sh/sh.opt (mcbranchdi, mcmpeqdi): Mark as undocumented and
emit a warning.
* config/sh/sh.c (sh_option_override): Initialize TARGET_CBRANCHDI4
and TARGET_CMPEQDI_T variables.
* doc/invoke.texi (SH options): Undocument -mcbranchdi and -mcmpeqdi.
testsuite/ChangeLog:
PR target/52898
PR target/51697
* gcc.target/sh/pr51697.c: New.
Index: gcc/common/config/sh/sh-common.c
===================================================================
--- gcc/common/config/sh/sh-common.c (revision 205784)
+++ gcc/common/config/sh/sh-common.c (working copy)
@@ -34,7 +34,6 @@
{ OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_mdiv_, "inv:minlat", 1 },
{ OPT_LEVELS_SIZE, OPT_mdiv_, SH_DIV_STR_FOR_SIZE, 1 },
{ OPT_LEVELS_0_ONLY, OPT_mdiv_, "", 1 },
- { OPT_LEVELS_SIZE, OPT_mcbranchdi, NULL, 0 },
/* We can't meaningfully test TARGET_SHMEDIA here, because -m
options haven't been parsed yet, hence we'd read only the
default. sh_target_reg_class will return NO_REGS if this is
Index: gcc/config/sh/sh.opt
===================================================================
--- gcc/config/sh/sh.opt (revision 205784)
+++ gcc/config/sh/sh.opt (working copy)
@@ -233,11 +233,11 @@
Assume that zero displacement conditional branches are fast
mcbranchdi
-Target Var(TARGET_CBRANCHDI4)
+Target Undocumented Var(TARGET_CBRANCHDI4) Warn(%qs is deprecated and has no effect)
Enable cbranchdi4 pattern
mcmpeqdi
-Target Var(TARGET_CMPEQDI_T)
+Target Undocumented Var(TARGET_CMPEQDI_T) Warn(%qs is deprecated and has no effect)
Emit cmpeqdi_t pattern even when -mcbranchdi is in effect.
mcut2-workaround
Index: gcc/config/sh/sh.c
===================================================================
--- gcc/config/sh/sh.c (revision 205784)
+++ gcc/config/sh/sh.c (working copy)
@@ -771,6 +771,11 @@
SUBTARGET_OVERRIDE_OPTIONS;
if (optimize > 1 && !optimize_size)
target_flags |= MASK_SAVE_ALL_TARGET_REGS;
+
+ /* Set default values of TARGET_CBRANCHDI4 and TARGET_CMPEQDI_T. */
+ TARGET_CBRANCHDI4 = 1;
+ TARGET_CMPEQDI_T = 0;
+
sh_cpu = PROCESSOR_SH1;
assembler_dialect = 0;
if (TARGET_SH2)
Index: gcc/testsuite/gcc.target/sh/pr51697.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51697.c (revision 0)
+++ gcc/testsuite/gcc.target/sh/pr51697.c (revision 0)
@@ -0,0 +1,21 @@
+/* Check that DImode comparisons are optimized as expected when compiling
+ with -Os. */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-times "tst" 2 } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+
+int
+test_00 (long long* x)
+{
+ /* 1x tst, no cmp/* insns. */
+ return *x & 0xFFFFFFFF ? -20 : -40;
+}
+
+int
+test_01 (unsigned long long x)
+{
+ /* 1x tst, no cmp/* insns. */
+ return x >= 0x100000000LL ? -20 : -40;
+}
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 205784)
+++ gcc/doc/invoke.texi (working copy)
@@ -959,7 +959,7 @@
-mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
-maccumulate-outgoing-args -minvalid-symbols @gol
-matomic-model=@var{atomic-model} @gol
--mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch -mcbranchdi -mcmpeqdi @gol
+-mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch @gol
-mfused-madd -mno-fused-madd -mfsca -mno-fsca -mfsrra -mno-fsrra @gol
-mpretend-cmove -mtas}
@@ -20252,15 +20252,6 @@
enabled by default when generating code for SH4 and SH4A. It can be explicitly
disabled by specifying @option{-mno-zdcbranch}.
-@item -mcbranchdi
-@opindex mcbranchdi
-Enable the @code{cbranchdi4} instruction pattern.
-
-@item -mcmpeqdi
-@opindex mcmpeqdi
-Emit the @code{cmpeqdi_t} instruction pattern even when @option{-mcbranchdi}
-is in effect.
-
@item -mfused-madd
@itemx -mno-fused-madd
@opindex mfused-madd
