From 4b3a4af17f0bc7eaea08332d34a4978a176b1a44 Mon Sep 17 00:00:00 2001 From: nagaraju Date: Tue, 12 Mar 2013 13:25:11 +0530 Subject: [PATCH 08/11] [Patch, microblaze]: Add optimized lshrsi3 When barrel shifter is not present, the immediate value is greater than #5 and optimization is -OS, the compiler will generate shift operation using loop. Changelog 2013-11-26 Nagaraju Mekala * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn Signed-off-by:Nagaraju Signed-off-by: David Holsgrove --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 41f27c0..0a563f9 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1542,6 +1542,27 @@ (set_attr "length" "4,4")] ) +(define_insn "*lshrsi3_with_size_opt" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "(INTVAL (operands[2]) > 5 && optimize_size)" + { + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + + output_asm_insn ("ori\t%3,r0,%2", operands); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,%1,r0", operands); + + output_asm_insn ("addik\t%3,%3,-1", operands); + output_asm_insn ("bneid\t%3,.-4", operands); + return "srl\t%0,%0"; + } + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "20")] +) + (define_insn "*lshrsi_inline" [(set (match_operand:SI 0 "register_operand" "=&d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") -- 1.7.9.5