"Maciej W. Rozycki" <[email protected]> writes:
> 2013-11-14 Maciej W. Rozycki <[email protected]>
>
> gcc/
> * config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64
> restriction for ISA_MIPS32R2.
> (ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
> (ISA_HAS_NMADD4_NMSUB4): Likewise.
> (ISA_HAS_FP_RECIP_RSQRT): Likewise.
> (ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4.
Nice.
So the reasoning is that, after your RECIP.fmt patch, the only direct uses
of ISA_HAS_FP4 for instruction selection are indexed loads and stores.
That's why extending them to ISA_MIPS32R2 && !TARGET_FLOAT64 allows
ISA_HAS_FP4 to be simplified. But if we keep:
> @@ -906,16 +906,14 @@ struct mips_cpu_info {
> #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
>
> /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
> -#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \
> - || (ISA_MIPS32R2 && !TARGET_MIPS16))
> +#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
>
> /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
> #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
>
> /* ISA has floating-point nmadd and nmsub instructions
> 'd = -((a * b) [+-] c)'. */
> -#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4
> \
> - || (ISA_MIPS32R2 && !TARGET_MIPS16))
> +#define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
then I think we should also have a macro like:
/* ISA has indexed floating-point loads and stores (LWXC1, LDXC1, SWXC1
and SDXC1). */
#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
and add:
Note that this macro should only be used by other ISA_HAS_* macros.
to the ISA_HAS_FP4 comment.
OK with those changes, thanks.
Richard
