Re: [PATCH] MIPS: MIPS32r2 FP reciprocal instruction set support

[Richard Sandiford]

"Maciej W. Rozycki" <ma...@codesourcery.com> writes:
>  Note that these instructions were allowed in either FPU mode in the MIPS 
> IV ISA, but for forward ISA compatibility this change does not enable them 
> for -march=mips4 in the 32-bit FPR mode because the original revision of 
> the MIPS64 ISA did not support it.

Yeah, sounds good.

> Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.h
> ===================================================================
> --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.h   2013-11-12 
> 15:31:46.758734464 +0000
> +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.h        2013-11-12 
> 15:33:22.277646941 +0000
> @@ -921,6 +921,21 @@ struct mips_cpu_info {
>     'c = -((a * b) [+-] c)'.  */
>  #define ISA_HAS_NMADD3_NMSUB3        TARGET_LOONGSON_2EF
>  
> +/* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions.  The
> +   MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
> +   doubles are stored in pairs of FPRs, so for safety's sake, we apply
> +   this restriction to the MIPS IV ISA too.  */
> +#define ISA_HAS_FP_RECIP_RSQRT(MODE)                                 \
> +                             (((ISA_HAS_FP4                          \
> +                                || (ISA_MIPS32R2 && !TARGET_MIPS16)) \
> +                               && ((MODE) == SFmode                  \
> +                                   || ((TARGET_FLOAT64               \
> +                                        || !(ISA_MIPS4               \
> +                                             || ISA_MIPS64))         \
> +                                       && (MODE) == DFmode)))        \
> +                              || ((TARGET_SB1 && !TARGET_MIPS16)     \
> +                                  && (MODE) == V2SFmode))

I think the !(ISA_MIPS4 || ISA_MIPS64) part is really "r2 or later",
which elsewhere we test as "ISA_MIPS32R2 || ISA_MIPS64R2".  Obviously
that isn't as future-proof, but I think consistency wins here.
(E.g. the earlier ISA_MIPS32R2 seems like it's reallly "r2 or later" too).

Cleaning up these macros has been on my todo list for about ten years :-(

Please also test !TARGET_MIPS16 at the outermost level, so that there's
only one instance.  I think that gives something like:

#define ISA_HAS_FP_RECIP_RSQRT(MODE)                                    \
                                ((((ISA_HAS_FP4 || ISA_MIPS32R2)        \
                                   && ((MODE) == SFmode                 \
                                       || ((TARGET_FLOAT64              \
                                            || ISA_MIPS32R2             \
                                            || ISA_MIPS64R2)            \
                                           && (MODE) == DFmode)))       \
                                  || (TARGET_SB1                        \
                                      && (MODE) == V2SFmode))           \
                                 && !TARGET_MIPS16)

OK with those changes, thanks.

Richard