On Tue, Sep 24, 2013 at 4:33 PM, Michael Meissner
<meiss...@linux.vnet.ibm.com> wrote:
> This patch adds the initial support for putting DI, DF, and SF values in the
> upper registers (traditional Altivec registers) using the -mupper-regs-df and
> -mupper-regs-sf patches. Those switches will not be enabled by default until
> the rest of the changes are made. This patch passes the bootstrap test and
> make check test. I tested all of the targets I tested previously (power4-8,
> G4/G5, SPE, cell, e5500/e5600, and paired floating point), and all machines
> generate the same code. Is it ok to install this patch?
>
> [gcc]
> 2013-09-24 Michael Meissner <meiss...@linux.vnet.ibm.com>
>
> * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
> DFmode, DImode, and SFmode in the upper VSX registers based on the
> -mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS
> if -mpower8-vector. Combine -mvsx-timode handling with the rest
> of the VSX register handling.
>
> * config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.
> (f32_sv): Likewise.
> (zero_extendsidi2_lfiwzx): Add support for loading into the
> Altivec registers with -mpower8-vector. Use wu/wv constraints to
> only do VSX memory options on Altivec registers.
> (extendsidi2_lfiwax): Likewise.
> (extendsfdf2_fpr): Likewise.
> (mov<mode>_hardfloat, SF/SD modes): Likewise.
> (mov<mode>_hardfloat32, DF/DD modes): Likewise.
> (mov<mode>_hardfloat64, DF/DD modes): Likewise.
> (movdi_internal64): Likewise.
>
> [gcc/testsuite]
> 2013-09-24 Michael Meissner <meiss...@linux.vnet.ibm.com>
>
> * gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf
> and -mupper-regs-df.
Okay.
Thanks, David
