> You're missing the point. If the programmer wrote two statements
> which hit volatile memory and you've got some pattern which matches
> those two statements, then with your change you'll end up combining
> them, that's wrong.
I see nothing in the ISO spec that says you can't combine a volatile
read/modify/write cycle into a single insn. The spec requires that
the volatile value is stable at sequence points, but does not (AFAICT)
require that the sequence point be between insns.
So even if the programmer wrote:
register int a;
extern volatile int b;
a = b;
a |= 0x54;
b = a;
The ISO spec seems to allow gcc to perform those operations in a
single physical insn, as long as the operations on 'b' are all
performed, and in the correct sequence.
