[patch, mips] Fix for loongson prefetching and -mabi=32

[Steve Ellcey]

Someone using buildroot reported a problem to me that I tracked down to
compiling a routine containing __builtin_prefetch with '-march=loongson
-mabi=32'.  When doing this the prefetch instruction on loongson generates
'ld' instead of 'lw' and then tries to put it into a delay slot.  This
causes the assembler to generate a warning both because 'ld' in 32 bit
mode is a macro and GCC put out a '.set nomacro' and because it tries to
put the two instructions generated by the macro into a delay slot.  My fix
is to generate 'lw' in 32 bit mode on loongson, then it doesn't generate a
macro and the instruction that is generated can go into a delay slot.

OK for checkin?


2013-08-12  Steve Ellcey  <sell...@mips.com>

        * config/mips/mips.md (prefetch): Use lw instead of ld on
        loongson in 32bit mode.


diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 397c40a..ad03040 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -6674,7 +6674,10 @@
 {
   if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
     /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching.  
*/
-    return "ld\t$0,%a0";
+    if (TARGET_64BIT)
+      return "ld\t$0,%a0";
+    else
+      return "lw\t$0,%a0";
   operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
   return "pref\t%1,%a0";
 }