On Fri, Jun 28, 2013 at 11:39:46AM -0400, David Edelsohn wrote:
> Only the PTI change is okay.
As we discussed over IRC, this is the patch that I committed.
[gcc]
2013-06-28 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/57744
* config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode
to tie with any other modes. Eliminate Altivec vector mode tests,
since these are a subset of ALTIVEC or VSX vector modes. Simplify
code, to return 0 if testing MODE2 for a condition, if we've
already tested MODE1 for the same condition.
[gcc/testsuite]
2013-06-28 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/57744
* gcc.target/powerpc/pr57744.c: New test to make sure lqarx and
stqcx. get even registers.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 200535)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -1180,28 +1180,32 @@ enum data_align { align_abi, align_opt,
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ for any hard reg, then this must be 0 for correct output.
+
+ PTImode cannot tie with other modes because PTImode is restricted to even
+ GPR registers, and TImode can go in any GPR as well as VSX registers (PR
+ 57744). */
#define MODES_TIEABLE_P(MODE1, MODE2) \
- (SCALAR_FLOAT_MODE_P (MODE1) \
+ ((MODE1) == PTImode \
+ ? (MODE2) == PTImode \
+ : (MODE2) == PTImode \
+ ? 0 \
+ : SCALAR_FLOAT_MODE_P (MODE1) \
? SCALAR_FLOAT_MODE_P (MODE2) \
: SCALAR_FLOAT_MODE_P (MODE2) \
- ? SCALAR_FLOAT_MODE_P (MODE1) \
+ ? 0 \
: GET_MODE_CLASS (MODE1) == MODE_CC \
? GET_MODE_CLASS (MODE2) == MODE_CC \
: GET_MODE_CLASS (MODE2) == MODE_CC \
- ? GET_MODE_CLASS (MODE1) == MODE_CC \
+ ? 0 \
: SPE_VECTOR_MODE (MODE1) \
? SPE_VECTOR_MODE (MODE2) \
: SPE_VECTOR_MODE (MODE2) \
- ? SPE_VECTOR_MODE (MODE1) \
+ ? 0 \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
: ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
- ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
- : ALTIVEC_VECTOR_MODE (MODE1) \
- ? ALTIVEC_VECTOR_MODE (MODE2) \
- : ALTIVEC_VECTOR_MODE (MODE2) \
- ? ALTIVEC_VECTOR_MODE (MODE1) \
+ ? 0 \
: 1)
/* Post-reload, we can't use any new AltiVec registers, as we already
Index: gcc/testsuite/gcc.target/powerpc/pr57744.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr57744.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr57744.c (revision 0)
@@ -0,0 +1,37 @@
+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+typedef unsigned U_16 __attribute__((mode(TI)));
+
+extern int libat_compare_exchange_16 (U_16 *, U_16 *, U_16, int, int)
+ __attribute__((__noinline__));
+
+/* PR 57744: lqarx/stqcx needs even/odd register pairs. The assembler will
+ complain if the compiler gets an odd/even register pair. Create a function
+ which has the 16 byte compare and exchange instructions, but don't actually
+ execute it, so that we can detect these failures on older machines. */
+
+int
+libat_compare_exchange_16 (U_16 *mptr, U_16 *eptr, U_16 newval,
+ int smodel, int fmodel __attribute__((unused)))
+{
+ if (((smodel) == 0))
+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 0, 0);
+ else if (((smodel) != 5))
+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 4, 0);
+ else
+ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 5, 0);
+}
+
+U_16 a = 1, b = 1, c = -2;
+volatile int do_test = 0;
+
+int main (void)
+{
+ if (do_test && !libat_compare_exchange_16 (&a, &b, c, 0, 0))
+ aborrt ();
+
+ return 0;
+}
