Hi all, This patch makes the changes to the various floating point patterns in vfp.md. Since pretty much all floating point instruction are always encoded in 32 bits, they cannot be used inside an IT block by the -mrestrict-it rules. Therefore this patch just goes and disables the predicable variants of the offending VFP patterns.
The conditional floating point move patterns are disabled altogether for
arm_restrict_it because they explicitly use IT blocks in their output
template and the corresponding expanders in arm.md are updated to make
sure we use the new vsel instruction that is available in ARMv8 when
appropriate.
Tested arm-none-eabi on qemu and model as part of the whole series and
also independently bootstrapped with -mrestrict-it enabled on a
Cortex-A15.
Ok for trunk?
Thanks,
Kyrill
2013-06-10 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/predicates.md (arm_cond_move_operator): New
predicate.
* config/arm/arm.md (movsfcc): Use arm_cond_move_operator
predicate.
(movdfcc): Likewise.
* config/arm/vfp.md (*thumb2_movsf_vfp):
Disable predication for arm_restrict_it.
(*thumb2_movsfcc_vfp): Disable for arm_restrict_it.
(*thumb2_movdfcc_vfp): Likewise.
(*abssf2_vfp, *absdf2_vfp, *negsf2_vfp, *negdf2_vfp,
*addsf3_vfp,
*adddf3_vfp, *subsf3_vfp, *subdf3_vfpc, *divsf3_vfp,
*divdf3_vfp,
*mulsf3_vfp, *muldf3_vfp, *mulsf3negsf_vfp, *muldf3negdf_vfp,
*mulsf3addsf_vfp, *muldf3adddf_vfp, *mulsf3subsf_vfp,
*muldf3subdf_vfp, *mulsf3negsfaddsf_vfp, *fmuldf3negdfadddf_vfp,
*mulsf3negsfsubsf_vfp, *muldf3negdfsubdf_vfp, *fma<SDF:mode>4,
*fmsub<SDF:mode>4, *fnmsub<SDF:mode>4, *fnmadd<SDF:mode>4,
*extendsfdf2_vfp, *truncdfsf2_vfp, *extendhfsf2, *truncsfhf2,
*truncsisf2_vfp, *truncsidf2_vfp, fixuns_truncsfsi2,
fixuns_truncdfsi2,
*floatsisf2_vfp, *floatsidf2_vfp, floatunssisf2, floatunssidf2,
*sqrtsf2_vfp, *sqrtdf2_vfp, *cmpsf_vfp, *cmpsf_trap_vfp,
*cmpdf_vfp,
*cmpdf_trap_vfp, <vrint_pattern><SDF:mode>2):
Disable predication for arm_restrict_it.
it-depr-vfp.patch
Description: Binary data
