This moves lshrsi3 over and merges it with lshrdi3. The immediate version is split off since it needs a different condition (and is a separate instruction anyway).
Tested as per usual; okay? 2013-05-31 Segher Boessenkool <seg...@kernel.crashing.org> gcc/ * config/rs6000/rs6000.md (lshrsi3): Delete. * config/rs6000/integer.mdm: (lshrdi3): Delete. (lshr<mode>3, lshr<mode>3_imm): New. * config/rs6000/integer.md: Regenerate. --- gcc/config/rs6000/integer.md | 177 +++++++++++++++++++++++++++++------------- gcc/config/rs6000/integer.mdm | 28 ++++--- gcc/config/rs6000/rs6000.md | 75 ------------------ 3 files changed, 143 insertions(+), 137 deletions(-) diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md index 0884e0f..2be1f35 100644 --- a/gcc/config/rs6000/integer.md +++ b/gcc/config/rs6000/integer.md @@ -32,90 +32,163 @@ ; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.] -(define_insn "lshrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" +(define_insn "lshr<mode>3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "sr<wd> %0,%1,%2" + [(set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_insn "*lshr<mode>3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "<MODE>mode == Pmode && rs6000_gen_cell_microcode" "@ - srd %0,%1,%2 - srdi %0,%1,%H2" - [(set_attr "type" "var_shift_rotate,shift") ; var_delayed_compare,delayed_compare + sr<wd>. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "(<MODE>mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*lshr<mode>3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "<MODE>mode == Pmode && rs6000_gen_cell_microcode" + "@ + sr<wd>. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(<MODE>mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*lshr<mode>3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" + "sr<wd>i %0,%1,%2" + [(set_attr "type" "shift") ; delayed_compare ]) -(define_insn "*lshrdi3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") +(define_insn "*lshr<mode>3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) (const_int 0))) - (clobber (match_scratch:DI 0 "=r,r,r,r"))] - "(TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)" + (clobber (match_scratch:GPR 0 "=r,r"))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)) + && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)" "@ - srd. %0,%1,%2 - srdi. %0,%1,%H2 - # + sr<wd>i. %0,%1,%2 #" - [(set_attr "length" "4,4,8,8") - (set_attr "dot" "yes,yes,no,no") - (set_attr "type" "var_shift_rotate,shift,var_shift_rotate,shift") ; var_delayed_compare,delayed_compare + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift") ; delayed_compare ]) (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) (const_int 0))) - (clobber (match_scratch:DI 0 ""))] - "((TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)) + (clobber (match_scratch:GPR 0 ""))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)) + && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)) && (reload_completed)" [(set (match_dup 0) - (lshiftrt:DI (match_dup 1) - (match_dup 2))) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn "*lshrdi3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") +(define_insn "*lshr<mode>3_imm_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (lshiftrt:DI (match_dup 1) - (match_dup 2)))] - "(TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)) + && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)" "@ - srd. %0,%1,%2 - srdi. %0,%1,%H2 - # + sr<wd>i. %0,%1,%2 #" - [(set_attr "length" "4,4,8,8") - (set_attr "dot" "yes,yes,no,no") - (set_attr "type" "var_shift_rotate,shift,var_shift_rotate,shift") ; var_delayed_compare,delayed_compare + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift") ; delayed_compare ]) (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (lshiftrt:DI (match_dup 1) - (match_dup 2)))] - "((TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)) + && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)) && (reload_completed)" [(set (match_dup 0) - (lshiftrt:DI (match_dup 1) - (match_dup 2))) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] diff --git a/gcc/config/rs6000/integer.mdm b/gcc/config/rs6000/integer.mdm index 23ff8ca..7dd68dc 100644 --- a/gcc/config/rs6000/integer.mdm +++ b/gcc/config/rs6000/integer.mdm @@ -28,16 +28,24 @@ ; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.] -(define_dot_insn "lshrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "DImode == Pmode && rs6000_gen_cell_microcode" - "@ - srd %0,%1,%2 - srdi %0,%1,%H2" - [(set_attr "type" "var_shift_rotate,shift") ; var_delayed_compare,delayed_compare +(define_dot_insn "lshr<mode>3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "<MODE>mode == Pmode && rs6000_gen_cell_microcode" + "sr<wd> %0,%1,%2" + [(set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_dot_insn "*lshr<mode>3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" + "<MODE>mode == Pmode && rs6000_gen_cell_microcode" + "sr<wd>i %0,%1,%2" + [(set_attr "type" "shift") ; delayed_compare ]) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7adde36..f28003d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4290,17 +4290,6 @@ (define_split (const_int 0)))] "") -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))] - "" - "@ - mr %0,%1 - srw %0,%1,%2 - srwi %0,%1,%h2" - [(set_attr "type" "integer,var_shift_rotate,shift")]) - (define_insn "*lshrsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI @@ -4313,70 +4302,6 @@ (define_insn "*lshrsi3_64" [(set_attr "type" "var_shift_rotate,shift")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))] - "TARGET_32BIT" - "@ - mr. %1,%1 - srw. %3,%1,%2 - srwi. %3,%1,%h2 - # - # - #" - [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,4,8,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 3) - (lshiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") - (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" - "@ - mr. %0,%1 - srw. %0,%1,%2 - srwi. %0,%1,%h2 - # - # - #" - [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,4,8,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 0) - (lshiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) -- 1.8.1.4