On Fri, May 17, 2013 at 7:38 AM, Gopalasubramanian, Ganesh <ganesh.gopalasubraman...@amd.com> wrote:
> Thank you Uros for the patch. Could you backport this to the 4.8.0? > > -----Original Message----- > From: Uros Bizjak [mailto:ubiz...@gmail.com] > Sent: Wednesday, May 15, 2013 11:16 PM > To: gcc-patches@gcc.gnu.org > Cc: Gopalasubramanian, Ganesh > Subject: [PATCH, i386]: Update processor_alias_table for missing PTA_PRFCHW > and PTA_FXSR flags > > Hello! > > Attached patch adds missing PTA_PRFCHW and PTA_FXSR flags to x86 processor > alias table. PRFCHW CPUID flag is shared with 3dnow prefetch flag, so some > additional logic is needed to avoid generating SSE prefetches for non-SSE > 3dNow! targets, while still generating full set of 3dnow prefetches on 3dNow! > targets. > > 2013-05-15 Uros Bizjak <ubiz...@gmail.com> > > * config/i386/i386.c (iy86_option_override_internal): Update > processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags. Add > PTA_POPCNT to corei7 entry and remove PTA_SSE from athlon-4 entry. > Do not enable SSE prefetch on non-SSE 3dNow! targets. Enable > TARGET_PRFCHW for TARGET_3DNOW targets. > * config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW instead > of TARGET_3DNOW. > (*prefetch_3dnow): Enable for TARGET_PRFCHW only. > > Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32} > and was committed to mainline SVN. The patch will be backported to 4.8 branch > in a couple of days. Done. I have also reverted athlon-4 change everywhere. It does have SSE after all. Uros.
