Hi,
The below patch adds expanders and insns for QI and HI mode for the RL78 target.
The QI mode uses a generic 'mulu' instruction supported by all variants, while
the HI mode creates insn for G13 and G14 target variants using hardware multiply
instructions.
Tested on hardware and simulator with no additional regressions.
Kindly review the same.
Thanks,
Kaushik
2013-05-15 Kaushik Phatak <kaushik.pha...@kpitcummins.com>
* config/rl78/rl78.md (mulqi3,mulhi3): New define_expands.
(mulqi3_rl78,mulhi3_rl78,mulhi3_g13): New define_insns.
Index: gcc/config/rl78/rl78.md
===================================================================
--- gcc/config/rl78/rl78.md (revision 198915)
+++ gcc/config/rl78/rl78.md (working copy)
@@ -235,6 +235,24 @@
[(set_attr "valloc" "macax")]
)
+(define_expand "mulqi3"
+ [(set (match_operand:QI 0 "register_operand" "=&v")
+ (mult:QI (match_operand:QI 1 "general_operand" "+vim")
+ (match_operand:QI 2 "nonmemory_operand" "vi")))
+ ]
+ "" ; mulu supported by all targets
+ ""
+)
+
+(define_expand "mulhi3"
+ [(set (match_operand:HI 0 "register_operand" "=&v")
+ (mult:HI (match_operand:HI 1 "general_operand" "+vim")
+ (match_operand:HI 2 "nonmemory_operand" "vi")))
+ ]
+ "! RL78_MUL_NONE"
+ ""
+)
+
(define_expand "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=&v")
(mult:SI (match_operand:SI 1 "nonmemory_operand" "vi")
@@ -244,6 +262,55 @@
""
)
+(define_insn "mulqi3_rl78"
+ [(set (match_operand:QI 0 "register_operand" "=&v")
+ (mult:QI (match_operand:QI 1 "general_operand" "+viU")
+ (match_operand:QI 2 "general_operand" "vi")))
+ ]
+ "" ; mulu supported by all targets
+ "; mulqi macro %0 = %1 * %2
+ mov a, %h1
+ mov x, a
+ mov a, %h2
+ mulu x ; ax = a * x
+ mov a, x
+ mov %h0, a
+ ; end of mulqi macro"
+)
+
+(define_insn "mulhi3_rl78"
+ [(set (match_operand:HI 0 "register_operand" "=&v")
+ (mult:HI (match_operand:HI 1 "general_operand" "+viU")
+ (match_operand:HI 2 "general_operand" "vi")))
+ ]
+ "RL78_MUL_RL78"
+ "; mulhi macro %0 = %1 * %2
+ movw ax, %h1
+ movw bc, %h2
+ mulhu ; bcax = bc * ax
+ movw %h0, ax
+ ; end of mulhi macro"
+)
+
+(define_insn "mulhi3_g13"
+ [(set (match_operand:HI 0 "register_operand" "=&v")
+ (mult:HI (match_operand:HI 1 "general_operand" "+viU")
+ (match_operand:HI 2 "general_operand" "vi")))
+ ]
+ "RL78_MUL_G13"
+ "; mulhi macro %0 = %1 * %2
+ mov a, #0x00
+ mov !0xf00e8, a ; MDUC
+ movw ax, %h1
+ movw 0xffff0, ax ; MDAL
+ movw ax, %h2
+ movw 0xffff2, ax ; MDAH
+ nop ; mdb = mdal * mdah
+ movw ax, 0xffff6 ; MDBL
+ movw %h0, ax
+ ; end of mulhi macro"
+)
+
;; 0xFFFF0 is MACR(L). 0xFFFF2 is MACR(H) but we don't care about it
;; because we're only using the lower 16 bits (which is the upper 16
;; bits of the result).
