> Please consider this as a reminder to review the patch posted at
> following link:-
> http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01374.html
>
> The patch is slightly modified to use CC_NZ mode instead of CC.
>
> Please review the patch and let me know if its okay?
>
Hi Naveen,
With the CC_NZ fix, the patch looks good apart from one thing:
the second "set" in each pattern should have the "=r,rk" constraint
rather than just "=r,r".
That said, I've attached a patch that provides more thorough test cases,
including execute ones. When you get commit approval (which will be
after GCC goes into stage 1 again) then I can add in the test
cases. You might as well run them now though, for more confidence
in your work.
BTW, I have an implementation of BICS that's been waiting for
GCC to hit stage 1. I'll send that out for review soon.
NOTE: I do not have maintainer powers here, so you need someone else
to give the OK to your patch.
Cheers,
Ian
diff --git a/gcc/testsuite/gcc.target/aarch64/ands1.c
b/gcc/testsuite/gcc.target/aarch64/ands1.c
new file mode 100644
index 0000000..e2bf956
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ands1.c
@@ -0,0 +1,150 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+ int d = a & b;
+
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+ int d = a & 0xff;
+
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, 255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+ int d = a & (b << 3);
+
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl
3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & b;
+
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & 0xff;
+
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, 255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & (b << 3);
+
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl
3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = ands_si_test1 (29, 4, 5);
+ if (x != 13)
+ abort();
+
+ x = ands_si_test1 (5, 2, 20);
+ if (x != 25)
+ abort();
+
+ x = ands_si_test2 (29, 4, 5);
+ if (x != 38)
+ abort();
+
+ x = ands_si_test2 (1024, 2, 20);
+ if (x != 1044)
+ abort();
+
+ x = ands_si_test3 (35, 4, 5);
+ if (x != 41)
+ abort();
+
+ x = ands_si_test3 (5, 2, 20);
+ if (x != 25)
+ abort();
+
+ y = ands_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+ abort();
+
+ y = ands_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort();
+
+ y = ands_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & 0xff) + 0x320000004ll + 0x505050505ll))
+ abort();
+
+ y = ands_di_test2 (0x130002900ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort();
+
+ y = ands_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & (0x064000008ll << 3))
+ + 0x064000008ll + 0x505050505ll))
+ abort();
+
+ y = ands_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ands2.c
b/gcc/testsuite/gcc.target/aarch64/ands2.c
new file mode 100644
index 0000000..c778a54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ands2.c
@@ -0,0 +1,156 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+ int d = a & b;
+
+ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" }
} */
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+ int d = a & 0x99999999;
+
+ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919"
} } */
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } }
*/
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+ int d = a & (b << 3);
+
+ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+,
lsl 3" } } */
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3"
} } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & b;
+
+ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" }
} */
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+,
-6148914691236517206" } } */
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+,
-6148914691236517206" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & (b << 3);
+
+ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+,
lsl 3" } } */
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3"
} } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = ands_si_test1 (29, 4, 5);
+ if (x != 13)
+ abort();
+
+ x = ands_si_test1 (5, 2, 20);
+ if (x != 25)
+ abort();
+
+ x = ands_si_test2 (29, 4, 5);
+ if (x != 34)
+ abort();
+
+ x = ands_si_test2 (1024, 2, 20);
+ if (x != 1044)
+ abort();
+
+ x = ands_si_test3 (35, 4, 5);
+ if (x != 41)
+ abort();
+
+ x = ands_si_test3 (5, 2, 20);
+ if (x != 25)
+ abort();
+
+ y = ands_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+ abort();
+
+ y = ands_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort();
+
+ y = ands_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & 0xaaaaaaaaaaaaaaaall) + 0x320000004ll +
0x505050505ll))
+ abort();
+
+ y = ands_di_test2 (0x540004100ll,
+ 0x320000004ll,
+ 0x805050205ll);
+ if (y != (0x540004100ll + 0x805050205ll))
+ abort();
+
+ y = ands_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & (0x064000008ll << 3))
+ + 0x064000008ll + 0x505050505ll))
+ abort();
+
+ y = ands_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
