I only changed DSI to GPR. This is semantically the same but more
common in the backend.
Tested on s390 and s390x with z196 and zEC12.
Please apply to mainline. Thanks!
Bye,
-Andreas-
gcc/config/s390/s390.md | 61 ++!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1 file changed, 3 insertions(+), 58 modifications(!)
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 393,398 ****
--- 393,401 ----
;; the same template.
(define_code_iterator SHIFT [ashift lshiftrt])
+ ;; This iterator allow r[ox]sbg to be defined with the same template
+ (define_code_iterator IXOR [ior xor])
+
;; This iterator and attribute allow to combine most atomic operations.
(define_code_iterator ATOMIC [and ior xor plus minus mult])
(define_code_iterator ATOMIC_Z196 [and ior xor plus])
***************
*** 3474,3488 ****
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
! ; and op1 with a mask being 1 for the selected bits and 0 for the rest
! (define_insn "*insv<mode>_or_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
! "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
--- 3477,3537 ----
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
! (define_insn "*r<noxa>sbg_<mode>_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (IXOR:GPR
! (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
! [(set_attr "op_type" "RIE")])
!
! (define_insn "*r<noxa>sbg_di_rotl"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
! (IXOR:DI
! (and:DI
! (rotate:DI
! (match_operand:DI 1 "nonimmediate_operand" "d")
! (match_operand:DI 3 "const_int_operand" ""))
! (match_operand:DI 2 "contiguous_bitmask_operand" ""))
! (match_operand:DI 4 "nonimmediate_operand" "0")))
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
! [(set_attr "op_type" "RIE")])
!
! (define_insn "*r<noxa>sbg_<mode>_srl"
! [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (IXOR:GPR
! (and:GPR
! (lshiftrt:GPR
! (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 4 "nonimmediate_operand" "0")))
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10
! && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
! INTVAL (operands[2]))"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
! [(set_attr "op_type" "RIE")])
!
! (define_insn "*r<noxa>sbg_<mode>_sll"
! [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (IXOR:GPR
! (and:GPR
! (ashift:GPR
! (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 4 "nonimmediate_operand" "0")))
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10
! && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
! INTVAL (operands[2]))"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
