On Mon, Dec 3, 2012 at 10:31 PM, Jakub Jelinek <ja...@redhat.com> wrote: > On Mon, Dec 03, 2012 at 10:18:56PM +0400, Konstantin Serebryany wrote: >> The LLVM implementation always used 32-byte alignment for stack redzones. >> I never actually did any performance checking on x86 (32-byte aligned >> vs 8-byte aligned), >> although I suspect 32-byte aligned redzones should be ~2x faster. > > Why? The 32-byte realigning has significant cost, plus often one > extra register is eaten (the DRAP register), even bigger cost on > non-i?86/x86_64 targets.
Maybe because my understanding of x86 is rather old (or plain wrong). I tried a micro benchmark on Xeon E5-2690 and unaligned strores are just slightly more expensive (< 10%). I'll do more benchmarks with the actual asan instrumentation ~ tomorrow. So, I guess we need to align the redzones conditionally for sparc, etc. --kcc > > Jakub
