From: Steven Bosscher <stevenb....@gmail.com> Date: Thu, 8 Nov 2012 01:19:11 +0100
> On Wed, Nov 7, 2012 at 11:39 PM, David Miller wrote: >> One idea that occurred to me was perhaps to extend >> define_register_constraint such that an extra condition can be >> specified. So for sparc's constraint "U" it would evaluate to >> GENERAL_REGS but also express the condition that the hard register >> must be even. > > I haven't looked at the details of this all, but there are ports that > use define_predicate to request an even-numbered register. See e.g. > frv and v850. I'm not sure if/how the RA takes predicates into account > when selecting a register. That would only influence instruction recognition. > (bfin uses define_register_constraints, but it has separate register > classes for the even-numbered registers, so apparently that's not for > multi-word hardregs like your case.) Right. >> diff --git a/gcc/config/sparc/constraints.md >> b/gcc/config/sparc/constraints.md >> index 2f8c6ad..440dc57 100644 >> --- a/gcc/config/sparc/constraints.md >> +++ b/gcc/config/sparc/constraints.md >> @@ -130,7 +130,43 @@ >> (match_code "mem") >> (match_test "memory_ok_for_ldd (op)"))) >> >> -;; Not needed in 64-bit mode >> +;; This awkward register constraint is necessary because it is not >> +;; possible to express the "must be even numbered regsiter" condition > > s/regsiter/register/ Thanks, I'll fix that.
