Thanks for explanation, I understand it. I fixed issue which you marked. Changelog is unchanged.
---
Best regards,
Andrey Turetskiy
On Tue, Oct 30, 2012 at 7:40 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Tue, Oct 30, 2012 at 3:47 PM, Andrey Turetskiy
> <andrey.turets...@gmail.com> wrote:
>> I changed the patch according Uros' remarks. Please, have a look.
>>
>> Changelog:
>>
>> 2012-10-30 Andrey Turetskiy <andrey.turets...@gmail.com>
>>
>> * config/i386/i386.c (bdesc_args): Rename
>> CODE_FOR_avx2_umulhrswv16hi3 to
>> CODE_FOR_avx2_pmulhrswv16hi3.
>> * config/i386/predicates.md (const1_operand): Extend for vectors.
>> * config/i386/sse.md (ssse3_avx2): Extend.
>> (ssedoublemode): Ditto.
>> (<sse2_avx2>_uavg<mode>3): Merge avx2_uavgv32qi3, sse2_uavgv16qi3,
>> avx2_uavgv16hi3 and sse2_uavgv8hi3 into one.
>> (*<sse2_avx2>_uavg<mode>3): Merge *avx2_uavgv32qi3, *sse2_uavgv16qi3,
>> *avx2_uavgv16hi3 and *sse2_uavgv8hi3 into one.
>> (PMULHRSW): New.
>> (<ssse3_avx2>_pmulhrsw<mode>3): Merge avx2_umulhrswv16hi3,
>> ssse3_pmulhrswv8hi3 and ssse3_pmulhrswv4hi3 into one.
>> (*avx2_pmulhrswv16hi3): Replace const_vector with match_operand.
>> (*ssse3_pmulhrswv8hi3): Ditto.
>> (*ssse3_pmulhrswv4hi3): Ditto.
>
> +{
> + ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
> + operands[3] = CONST1_RTX(<MODE>mode);
> +})
>
> Please put operands[3] initialization before the call to
> ix86_f_b_o_n_c. We don't want to pass uninitialized operands around.
>
> +{
> + if (which_alternative == 0
> + && (<MODE>mode == V16QImode
> + || <MODE>mode == V8HImode))
> + return "pavg<ssemodesuffix>\t{%2, %0|%0, %2}";
> + return "vpavg<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}";
> +}
> + [(set (attr "isa")
> + (if_then_else
> + (match_test "which_alternative == 0 && (<MODE>mode ==
> V16QImode || <MODE>mode == V8HImode)")
> + (const_string "noavx")
> + (const_string "avx")))
> + (set (attr "prefix_data16")
> + (if_then_else (eq_attr "isa" "noavx")
> + (const_string "1")
> + (const_string "*")))
> + (set (attr "prefix")
> + (if_then_else (eq_attr "isa" "noavx")
> + (const_string "orig")
> + (const_string "vex")))
>
> Uh, oh.
>
> Please note that "isa" attribute enables or disables the alternative
> through "enabled" attribute. Just change the "mode" attribute to
> "<sseinsnmode>" and everything will magically work:
> - AVX2 implies AVX, so it enables alternative 1, while disabling
> alternative 0 (and vice versa when AVX is disabled through noavx isa
> attribute).
> - Correct modes are conditionally enabled via VI12_AVX2 iterator
> - Base ISA level is enabled via insn predicate (TARGET_SSE2).
>
> You have to track three dependant conditions to calculate how insn
> pattern/mode/operand predicate are enabled ;)
>
> Uros,
const_vector_replace.patch
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